coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2020-12-04	soc/intel/{skl,cnl}: add NMI_{EN,STS} registers	Michael Niewöhner
2020-09-27	soc/intel/cannonlake: Align gpio_op.asl with TGL	Subrata Banik
2020-05-11	treewide: Remove "this file is part of" lines	Patrick Georgi
2020-04-06	soc/intel/cannonlake: Use SPDX for GPL-2.0-only files	Angel Pons
2020-03-18	soc: Remove copyright notices	Patrick Georgi
2019-04-29	soc/intel: Add GPI interrupt config register offset info	Karthikeyan Ramasubramanian
2019-03-04	soc/intel/cannonlake: Move common definitions to a header file	Rizwan Qureshi
2019-02-27	soc/intel/cannonlake: Add ASL functions to manipulate RX/TX buffers	Rizwan Qureshi
2019-02-22	soc/intel/cannonlake: Add ASL function for setting pad mode	Rizwan Qureshi
2019-01-03	soc/intel/cannonlake: Add cannonlake ACPI GPIO op	Lijian Zhao
2018-10-17	soc/intel/cannonlake: Add CNP PCH-H gpio pin definitions	praveen hodagatta pranesh