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path: root/src/soc/intel/cannonlake/fsp_params.c
AgeCommit message (Expand)Author
2020-08-23soc/intel/cnl: Configure FSP option PcieRpSlotImplementedNico Huber
2020-08-07soc/intel/cnl: Set Heci1Disable depending on devicetree configFelix Singer
2020-07-28soc/intel/cannonlake: Configure SataPwrOptEnable only if SATA is enabledFelix Singer
2020-07-26src: Update bare access to BOOL CONFIG_ vals to CONFIG()Martin Roth
2020-07-20soc/intel/cannonlake: Add configs for USB 3.1 Gen2 EV settingsJamie Chen
2020-07-01soc/intel/cannonlake: make satahotplug user configurable via devicetreeJonas Loeffelholz
2020-06-25soc/intel/cannonlake: Add PchPmPwrCycDur to chip optionsSridhar Siricilla
2020-06-02soc/intel/cannonlake: Add RP configuration settingsChristian Walter
2020-05-26cannonlake: update processor power limits configurationSumeet R Pawnikar
2020-05-26soc/intel/cannonlake: Add VrPowerDeliveryDesign to chip optionsChristian Walter
2020-05-11treewide: Remove "this file is part of" linesPatrick Georgi
2020-04-06soc/intel/cannonlake: Use SPDX for GPL-2.0-only filesAngel Pons
2020-03-18soc: Remove copyright noticesPatrick Georgi
2020-03-17soc/intel/cannonlake: Set correct serirq modeJeremy Soller
2020-02-28soc/intel/cannonlake: Plumb TetonGlacierMode into dtEdward O'Callaghan
2020-02-26soc/intel/{cnl,icl}: Avoid static 8254 clock gating on S3 resumeSubrata Banik
2019-12-19{drivers,soc}/intel/fsp2_0: Move chipset specific logo handling to SoCWim Vervoorn
2019-11-27soc/intel/cannonlake: Disable USB2 PHY Power gatingSurendranath Gurivireddy
2019-10-30soc/intel/cannonlake: set FSP param to enable or skip GOPMichael Niewöhner
2019-10-22soc/intel/cannonlake: Fix FSP UPDs settings with disabled GBEKane Chen
2019-10-02soc/intel: Replace config_of_path() with config_of_soc()Kyösti Mälkki
2019-09-12soc/intel/cnl: Remove unnecessary FSP UPD “PchPwrOptEnable” usageSubrata Banik
2019-09-12soc/intel/cannonlake: Add config for sata devslp pad reset configurationAamir Bohra
2019-09-09soc/intel/cannonlake: Allow coreboot to handle SPI lockdownSubrata Banik
2019-09-09soc/intel/cannonlake: Add ability to disable Heci1Bora Guvendik
2019-08-26soc/intel/cannonlake: Add config to disable display audio codecAamir Bohra
2019-08-20soc/intel/cnl: Add provision to configure SD controller write protect pinAamir Bohra
2019-08-05soc/intel/{cnl,icl}: Add support to get LPSS controllers list from SOCAamir Bohra
2019-08-02soc/intel/cannonlake: Disable ACPI PM timer to reduce S0ix power usageSubrata Banik
2019-07-30soc/intel/cannonlake: Allow coreboot to handle required chipset lockdownSubrata Banik
2019-07-29soc/intel/cannonlake: Correct the data type of serial_io_devAamir Bohra
2019-07-18soc/intel: Use config_of_path(SA_DEVFN_ROOT)Kyösti Mälkki
2019-07-13soc/intel/cnl: Sync CONFIG_LPSS_UART_FOR_CONSOLE with FSPNico Huber
2019-07-04soc/intel: Replace uses of dev_find_slot()Kyösti Mälkki
2019-06-28soc/intel/cannonlake: fix use of legacy 8254 timerMatt DeVillier
2019-05-20soc/intel/cannonlake: Configure SPI CS parameters in FSP UPD.Tim Wawrzynczak
2019-05-01mb/google/sarien: Disable S5 wake on LAN by defaultEric Lai
2019-04-26soc/{amd,intel}/chip: Use local include for chip.hElyes HAOUAS
2019-04-23soc/intel/cannonlake: Add null reference check for Cnvi and XdciAamir Bohra
2019-04-22Revert "soc/intel/cannonlake: Enable coreboot MP PPI service for WHL/CML"Lijian Zhao
2019-04-16soc/intel/cannonlake: Enable coreboot MP PPI service for WHL/CMLSubrata Banik
2019-04-08Replace remaining IS_ENABLED(CONFIG_*) with CONFIG()Nico Huber
2019-04-01soc/intel/cannonlake: Add FSP UPD to unlock GPIO pads in devicetreeKrishna Prasad Bhat
2019-03-29soc/intel/cannonlake: Ignore GBE LTRLijian Zhao
2019-03-27soc/intel/cannonlake: Configure voltage margining policiesKrzysztof Sywula
2019-03-21soc/intel/cannonlake: Assign FSP UPDs for HPD and Data/CLK of DDI portsKrishna Prasad Bhat
2019-03-20soc/intel/cannonlake: Fix return values for get_param_valueFurquan Shaikh
2019-03-16soc/intel/cannonlake: Add required FSP UPD changes for CMLSubrata Banik
2019-03-08coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)Julius Werner
2019-02-27soc/intel/cannonlake: Add a config for configuring SD_VDD1_PWR_EN#Rizwan Qureshi
2019-02-22soc/intel/cannonlake: Add support for setting FSP-S PcieRpHotPlug from device...Jeremy Soller
2019-02-21src/soc/intel/cannonlake: Add PsysPmax settingGaggery Tsai
2019-02-13soc/intel/cannonlake: Configure serial debug uartRonak Kanabar
2019-01-14soc/intel/cannonlake: Provide interface to update TCC offsetJohn Su
2019-01-08soc/intel/cannonlake: Add FSP UPD for minimum assertion widthDuncan Laurie
2019-01-01soc/intel/cannonlake: Enable CNVi based on devicetreeMaulik V Vaghela
2018-12-19soc/intel/cannonlake: SATA and DMI power optimizeLijian Zhao
2018-12-19soc/intel/cannonlake: Add Acoustic featuresLijian Zhao
2018-11-17soc/intel/cannonlake: Add options for pcie ltrLijian Zhao
2018-11-05soc/intel/cannonlake: Remove depreciated UPD selectionLijian Zhao
2018-10-09soc/intel/cannonlake: Disable Legacy PME for Root portsSubrata Banik
2018-10-08Move compiler.h to commonlibNico Huber
2018-10-04soc/intel/cannonlake: Move the FSP related callbacks to separate filesRizwan Qureshi