| Age | Commit message (Expand) | Author |
|---|---|---|
| 2017-08-30 | soc/intel/cannonlake: Add PrmrrSize and C6DRAM config | Subrata Banik |
| 2017-08-25 | soc/intel/cannonlake: Init UPD params based on config | Pratik Prajapati |
| 2017-08-22 | soc/intel/cannonlake: Define soc_intel_cannonlake_config | Pratik Prajapati |
| 2017-08-21 | soc/intel/cannonlake: Enable common PMC code for CNL | Lijian Zhao |
| 2017-08-17 | soc/intel/cannonlake: Add SPI flash controller driver | Lijian Zhao |
| 2017-08-15 | soc/intel/cannonlake: Call into FSP siliconinit | Lijian Zhao |
| 2017-07-21 | Revert "soc/intel/cannonlake: Call into FSP siliconinit" | Martin Roth |
| 2017-07-21 | soc/intel/cannonlake: Call into FSP siliconinit | Lijian Zhao |
 |
index : coreboot.git | |
| my copy of coreboot | User & |
| summaryrefslogtreecommitdiff |