diff options
| author | Lijian Zhao <lijian.zhao@intel.com> | 2017-08-16 22:18:52 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-08-21 20:37:57 +0000 |
| commit | b3dfcb863cdc62cd2cb65e97e0043311b151c558 (patch) | |
| tree | 1fbd8b130d79599f82212e719781d52f6b5e32c2 /src/soc/intel/cannonlake/chip.h | |
| parent | 7a357eb8657fd891aad33fd710d2f9d4d80c9130 (diff) | |
soc/intel/cannonlake: Enable common PMC code for CNL
This update changes Cannonlake to use the new common PMC code. This
will help to reduce code duplication and streamline code bring up.
Change-Id: Ia69fee8985e1c39b0e4b104c51439bca1a5493ac
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21062
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/cannonlake/chip.h')
| -rw-r--r-- | src/soc/intel/cannonlake/chip.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 67be85dd25..38f9a1ff7b 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -24,6 +24,13 @@ struct soc_intel_cannonlake_config { /* GSPI */ struct gspi_cfg gspi[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]; + + /* Gpio group routed to each dword of the GPE0 block. Values are + * of the form GPP_[A:G] or GPD. */ + uint8_t gpe0_dw0; /* GPE0_31_0 STS/EN */ + uint8_t gpe0_dw1; /* GPE0_63_32 STS/EN */ + uint8_t gpe0_dw2; /* GPE0_95_64 STS/EN */ + }; typedef struct soc_intel_cannonlake_config config_t; |