coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2018-12-19	soc: Remove useless include <device/pci_ids.h>	Elyes HAOUAS
2018-11-21	soc/intel/cannonlake: Fix IO decode setup	Duncan Laurie
2018-08-30	soc/intel/cannonlake: Update PMC base address for CNP H and LP	Maulik V Vaghela
2018-08-20	soc/intel/common/block: Move common uart function to block/uart	Subrata Banik
2018-06-28	soc/intel/common/block: Move p2sb common functions into block/p2sb	Subrata Banik
2018-06-14	src: Use of device_t is deprecated	Elyes HAOUAS
2018-01-25	soc/intel/cannonlake: enable pch link in bootblock	Caveh Jalali
2018-01-16	soc/intel/cannonlake: Program DMI PCR settings	Lijian Zhao
2018-01-10	soc/intel/cannonlake: Add a call to gspi_early_bar_init in bootblock	Furquan Shaikh
2018-01-05	soc/intel/cannonlake: Correct PMC/GPIO routing information	Lijian Zhao
2017-10-19	soc/intel/cannonlake: Fix HECI error on reset	Lijian Zhao
2017-10-18	soc/intel/cannonlake: Use EBDA area to store cbmem_top address	Subrata Banik
2017-08-21	soc/intel/cannonlake: Enable common PMC code for CNL	Lijian Zhao
2017-08-07	soc/intel/cannonlake: Add memory map support	Lijian Zhao
2017-07-18	soc/intel/cannonlake: Fix Build break	Lijian Zhao
2017-07-13	soc/intel/cannonlake: Add bootblock PCH	Andrey Petrov