coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2019-12-26	soc/intel/cannonlake: Refactor pch_early_init() code	Usha P
2019-12-02	soc/intel/cannonlake: Fix compilation	Praveen Hodagatta Pranesh
2019-11-26	soc/intel/{apl,cnl,dnv,skl}: Skip ucode loading by FSP-T	Subrata Banik
2019-08-26	lib/bootblock: Add simplified entry with basetime	Kyösti Mälkki
2019-08-01	soc/intel/cannonlake/bootblock: Clear the GPI IS & IE registers	David Wu
2019-03-08	coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)	Julius Werner
2019-01-09	soc/intel: Clean mess around UART_DEBUG	Nico Huber
2018-12-03	soc/intel/cannonlake: Load FSP teardown optionally	Lijian Zhao
2018-10-25	soc/intel: Consolidate FSP CAR setup and teardown code	Praveen hodagatta pranesh
2018-08-20	soc/intel/common/block: Move common uart function to block/uart	Subrata Banik
2018-05-22	bootblock: Allow more timestamps in bootblock_main_with_timestamp()	Julius Werner
2017-07-18	soc/intel/cannonlake: Fix Build break	Lijian Zhao
2017-07-02	soc/intel/cannonlake: Add bootblock.c	Andrey Petrov