| Age | Commit message (Expand) | Author |
|---|---|---|
| 2017-10-05 | soc/intel/cannonlake: Add all the SOC level DSDT tables | Lijian Zhao |
| 2017-10-03 | soc/intel/cannonlake: add initial ASL methods for SCS, GPIO | Bora Guvendik |
| 2017-09-19 | soc/intel/cannonlake: Add PCIE IRQs | Bora Guvendik |
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index : coreboot.git | |
| my copy of coreboot | User & |
| summaryrefslogtreecommitdiff |