coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2020-05-11	treewide: Remove "this file is part of" lines	Patrick Georgi
2020-05-06	treewide: replace GPLv2 long form headers with SPDX header	Patrick Georgi
2020-05-06	treewide: Move "is part of the coreboot project" line in its own comment	Patrick Georgi
2020-03-18	soc: Remove copyright notices	Patrick Georgi
2019-12-02	soc/intel/cannonlake: Add gfx.asl file	Mathew King
2019-11-01	soc/intel/{apl,cnl,dnv,icl,skl}: Move lpc.asl into common/block/acpi	Subrata Banik
2019-07-13	soc/intel/cannonlake: Remove unused header files from southbridge.asl	Aamir Bohra
2019-03-08	coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)	Julius Werner
2019-03-04	soc/intel/cnl/acpi: add ish ACPI device	Jett Rink
2018-11-15	soc/intel/cannonlake: Make static IRQ mapping for CNP PCH pci devices	Subrata Banik
2018-11-07	mb/{intel/google}: Move CNVi ASL entry from static DSDT to dynamic SSDT gener...	Subrata Banik
2018-10-17	soc/intel/cannonlake: Add CNP PCH-H gpio pin definitions	praveen hodagatta pranesh
2018-10-09	soc/intel/cannonlake: Add PCIE ASL entry	Subrata Banik
2018-10-09	soc/intel/cannonlake: Make correct IRQ mapping for CNL SA and PCH PCI devices	Subrata Banik
2018-09-28	soc/intel/cannonlake: Add ACPI entry for LAN	Lijian Zhao
2018-08-30	soc/intel/cannonlake: Fix comment errors for SMBUS	Lijian Zhao
2018-02-22	soc/intel/cannonlake: Clear EMMC timeout register	Lijian Zhao
2018-02-16	soc/intel/cannonlake: Use common PCR ASL	Lijian Zhao
2017-12-13	src/soc/intel/cannonlake: Add _PRW for CNVi	Bora Guvendik
2017-10-05	soc/intel/cannonlake: Add all the SOC level DSDT tables	Lijian Zhao
2017-10-03	soc/intel/cannonlake: add initial ASL methods for SCS, GPIO	Bora Guvendik
2017-09-19	soc/intel/cannonlake: Add PCIE IRQs	Bora Guvendik