| Age | Commit message (Expand) | Author |
|---|---|---|
| 2018-11-07 | mb/{intel/google}: Move CNVi ASL entry from static DSDT to dynamic SSDT gener... | Subrata Banik |
| 2018-10-17 | soc/intel/cannonlake: Add CNP PCH-H gpio pin definitions | praveen hodagatta pranesh |
| 2018-10-09 | soc/intel/cannonlake: Add PCIE ASL entry | Subrata Banik |
| 2018-10-09 | soc/intel/cannonlake: Make correct IRQ mapping for CNL SA and PCH PCI devices | Subrata Banik |
| 2018-09-28 | soc/intel/cannonlake: Add ACPI entry for LAN | Lijian Zhao |
| 2018-08-30 | soc/intel/cannonlake: Fix comment errors for SMBUS | Lijian Zhao |
| 2018-02-22 | soc/intel/cannonlake: Clear EMMC timeout register | Lijian Zhao |
| 2018-02-16 | soc/intel/cannonlake: Use common PCR ASL | Lijian Zhao |
| 2017-12-13 | src/soc/intel/cannonlake: Add _PRW for CNVi | Bora Guvendik |
| 2017-10-05 | soc/intel/cannonlake: Add all the SOC level DSDT tables | Lijian Zhao |
| 2017-10-03 | soc/intel/cannonlake: add initial ASL methods for SCS, GPIO | Bora Guvendik |
| 2017-09-19 | soc/intel/cannonlake: Add PCIE IRQs | Bora Guvendik |
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index : coreboot.git | |
| my copy of coreboot | User & |
| summaryrefslogtreecommitdiff |