| Age | Commit message (Expand) | Author |
|---|---|---|
| 2017-08-15 | soc/intel/cannonlake: Call into FSP siliconinit | Lijian Zhao |
| 2017-08-15 | soc/intel/cannonlake: Add postcar stage support | Lijian Zhao |
| 2017-08-09 | soc/intel/cannonlake: Add ramstage SystemAgent support | Lijian Zhao |
| 2017-08-07 | soc/intel/cannonlake: Add memory map support | Lijian Zhao |
| 2017-07-21 | Revert "soc/intel/cannonlake: Add postcar stage support" | Martin Roth |
| 2017-07-21 | Revert "soc/intel/cannonlake: Call into FSP siliconinit" | Martin Roth |
| 2017-07-21 | soc/intel/cannonlake: Call into FSP siliconinit | Lijian Zhao |
| 2017-07-21 | soc/intel/cannonlake: Add postcar stage support | Lijian Zhao |
| 2017-07-19 | soc/intel/cannonlake: Add minimal changes to call FSP Memoryinit | Lijian Zhao |
| 2017-07-19 | soc/intel/cannonlake: Add microcode support | Lijian Zhao |
| 2017-07-13 | soc/intel/cannonlake: Add Makefile | Andrey Petrov |
| 2017-06-29 | soc/intel/cannonlake: Add initial dummy directory | Lijian Zhao |
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index : coreboot.git | |
| my copy of coreboot | User & |
| summaryrefslogtreecommitdiff |