| Age | Commit message (Expand) | Author |
|---|---|---|
| 2017-08-21 | soc/intel/cannonlake: Enable common PMC code for CNL | Lijian Zhao |
| 2017-08-21 | soc/intel/cannonlake: Add Kconfig option to select UART index | Subrata Banik |
| 2017-08-17 | soc/intel/cannonlake: Add SPI flash controller driver | Lijian Zhao |
| 2017-08-15 | soc/intel/cannonlake: Add postcar stage support | Lijian Zhao |
| 2017-08-11 | soc/cannonlake: Enable SMM code for Cannon Lake | Brandon Breitenstein |
| 2017-08-03 | soc/intel/cannonlake: Sort Kconfig for Cannonlake | Lijian Zhao |
| 2017-07-21 | Revert "soc/intel/cannonlake: Add postcar stage support" | Martin Roth |
| 2017-07-21 | soc/intel/cannonlake: Add postcar stage support | Lijian Zhao |
| 2017-07-20 | soc/intel/cannonlake: Make ramstage relocatable | Lijian Zhao |
| 2017-07-19 | soc/intel/cannonlake: Add microcode support | Lijian Zhao |
| 2017-07-18 | soc/intel/cannonlake: Use common GPIO driver | Andrey Petrov |
| 2017-07-13 | soc/intel/cannonlake: Add early CPU initialization | Andrey Petrov |
| 2017-06-29 | soc/intel/cannonlake: Add initial dummy directory | Lijian Zhao |
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index : coreboot.git | |
| my copy of coreboot | User & |
| summaryrefslogtreecommitdiff |