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path: root/src/soc/intel/broadwell/romstage/cache_as_ram.inc
AgeCommit message (Expand)Author
2018-09-18cpu/*/car: fix ancient URL explaining XIP range run-time calculationStefan Tauner
2018-06-27x86/car: Replace reference of copy_and_run locationKyösti Mälkki
2017-06-07Use more secure HTTPS URLs for coreboot sitesPaul Menzel
2016-07-31src/soc: Capitalize CPU, ACPI, RAM and ROMElyes HAOUAS
2016-06-19intel/broadwell: Remove old USBDEBUG backup store in CARKyösti Mälkki
2016-06-18intel cache_as_ram: Fix typo in commentKyösti Mälkki
2016-06-17Fix some cbmem.h includesKyösti Mälkki
2015-10-31tree: drop last paragraph of GPL copyright headerPatrick Georgi
2015-10-15cpu/mtrr.h: Fix macro names for MTRR registersAlexandru Gagniuc
2015-08-25Intel: Remove CACHE_MRC_BIN - 'selected' everywhere in KconfigMartin Roth
2015-07-07x86: Drop -Wa,--divideStefan Reinauer
2015-06-08Remove empty lines at end of fileElyes HAOUAS
2015-05-21Remove address from GPLv2 headersPatrick Georgi
2015-04-04Broadwell: Pass TSC value to romstage_mainLee Leahy
2014-12-31broadwell: Preparations for buildingMarc Jones
2014-10-22broadwell: add new intel SOCDuncan Laurie
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