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coreboot.git
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mbp101_medisable
mbp101_medisable_1
mbp82
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my copy of coreboot
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intel
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broadwell
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romstage
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cache_as_ram.inc
Age
Commit message (
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Author
2018-12-05
soc/intel/broadwell: Implement postcar stage
Arthur Heymans
2018-09-18
cpu/*/car: fix ancient URL explaining XIP range run-time calculation
Stefan Tauner
2018-06-27
x86/car: Replace reference of copy_and_run location
Kyösti Mälkki
2017-06-07
Use more secure HTTPS URLs for coreboot sites
Paul Menzel
2016-07-31
src/soc: Capitalize CPU, ACPI, RAM and ROM
Elyes HAOUAS
2016-06-19
intel/broadwell: Remove old USBDEBUG backup store in CAR
Kyösti Mälkki
2016-06-18
intel cache_as_ram: Fix typo in comment
Kyösti Mälkki
2016-06-17
Fix some cbmem.h includes
Kyösti Mälkki
2015-10-31
tree: drop last paragraph of GPL copyright header
Patrick Georgi
2015-10-15
cpu/mtrr.h: Fix macro names for MTRR registers
Alexandru Gagniuc
2015-08-25
Intel: Remove CACHE_MRC_BIN - 'selected' everywhere in Kconfig
Martin Roth
2015-07-07
x86: Drop -Wa,--divide
Stefan Reinauer
2015-06-08
Remove empty lines at end of file
Elyes HAOUAS
2015-05-21
Remove address from GPLv2 headers
Patrick Georgi
2015-04-04
Broadwell: Pass TSC value to romstage_main
Lee Leahy
2014-12-31
broadwell: Preparations for building
Marc Jones
2014-10-22
broadwell: add new intel SOC
Duncan Laurie