coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2021-01-01	nb/intel/hsw,soc/intel/{bdw,skl,apl},mb/*: unify dt panel settings	Michael Niewöhner
2021-01-01	soc/intel/bdw,nb/intel/hsw: convert panel delays to ms representation	Michael Niewöhner
2020-10-30	soc/intel/broadwell: Separate PCH in devicetree	Angel Pons
2020-10-30	Revert "broadwell: update processor power limits configuration"	Angel Pons
2020-09-27	soc/intel/*/chip.h: Use `uint32_t` for `tcc_offset`	Angel Pons
2020-09-08	soc/intel/broadwell: Drop `gpu_panel_port_select`	Angel Pons
2020-07-28	broadwell: Factor out PIRQ routing from devicetree	Angel Pons
2020-05-18	broadwell: update processor power limits configuration	Sumeet R Pawnikar
2020-05-11	treewide: Remove "this file is part of" lines	Patrick Georgi
2020-04-06	soc/intel/broadwell: Use SPDX for GPL-2.0-only files	Angel Pons
2020-04-02	soc/intel/broadwell: add ACPI backlight support	Matt DeVillier
2020-03-18	soc: Remove copyright notices	Patrick Georgi
2019-10-16	intel/broadwell: Implement proper backlight PWM config	Nico Huber
2019-08-20	devicetree: Remove duplicate chip_ops declarations	Kyösti Mälkki
2018-11-01	src: Add missing include <stdint.h>	Elyes HAOUAS
2017-02-22	Broadwell/Sata: Add support for setting IOBP registers for Ports 2 and 3.	Youness Alaoui
2015-10-31	tree: drop last paragraph of GPL copyright header	Patrick Georgi
2015-05-21	Remove address from GPLv2 headers	Patrick Georgi
2015-04-10	broadwell: Add configuration for tuning VR for C-state operations	Duncan Laurie
2015-04-02	broadwell: Disable ADSP power gating feature by default	Duncan Laurie
2015-03-27	broadwell: Misc updates from 2.1.0 ref code	Duncan Laurie
2015-03-27	broadwell: Add config option to disable DSP power gating in D3	Duncan Laurie
2014-10-22	broadwell: add new intel SOC	Duncan Laurie