| Age | Commit message (Expand) | Author |
|---|---|---|
| 2016-01-14 | soc/braswell: Add CPUID for D0 stepping | Divya Sasidharan |
| 2015-10-31 | tree: drop last paragraph of GPL copyright header | Patrick Georgi |
| 2015-10-27 | FSP 1.1: Move common FSP code | Lee Leahy |
| 2015-10-15 | cpu/mtrr.h: Fix macro names for MTRR registers | Alexandru Gagniuc |
| 2015-08-29 | intel/braswell: allow dirty cache line evictions for SMRAM to stick | Chiranjeevi Rapolu |
| 2015-07-06 | Braswell: Update to end of June. | Lee Leahy |
| 2015-06-25 | Braswell: Add Braswell SOC support | Lee Leahy |
| 2015-05-28 | Remove address from GPLv2 headers | Patrick Georgi |
| 2015-05-23 | Braswell: Use Baytrail as Comparison Base | Lee Leahy |
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index : coreboot.git | |
| my copy of coreboot | User & |
| summaryrefslogtreecommitdiff |