coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2022-12-23	tree: Replace And(a,b,c) with ASL 2.0 syntax	Felix Singer
2022-12-23	tree: Replace Or(a,b,c) with ASL 2.0 syntax	Felix Singer
2022-12-14	soc/intel/braswell/acpi: Replace Store(a,b) with ASL 2.0 syntax	Felix Singer
2022-12-12	soc/intel/braswell/acpi: Replace LEqual(a,b) with ASL 2.0 syntax	Felix Singer
2020-05-11	treewide: Remove "this file is part of" lines	Patrick Georgi
2020-04-06	soc/intel/braswell: Use SPDX for GPL-2.0-only files	Angel Pons
2020-03-18	soc: Remove copyright notices	Patrick Georgi
2019-04-23	soc/intel/braswell/acpi/lpss.asl: Remove SPI1 and PWM asl code	Frans Hendriks
2017-06-09	soc/braswell: assign unique DMA request lines to I2C controllers	Matt DeVillier
2016-01-19	Braswell: add code to support customization of I2C data hold time	Kane Chen
2015-10-31	tree: drop last paragraph of GPL copyright header	Patrick Georgi
2015-06-25	Braswell: Add Braswell SOC support	Lee Leahy
2015-05-28	Remove address from GPLv2 headers	Patrick Georgi
2015-05-23	Braswell: Use Baytrail as Comparison Base	Lee Leahy