coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2022-12-14	soc/intel/braswell/acpi: Replace Store(a,b) with ASL 2.0 syntax	Felix Singer
2022-12-12	soc/intel/acpi: Replace Multiply(a,b,c) with ASL 2.0 syntax	Felix Singer
2022-12-12	soc/intel/acpi: Replace Subtract(a,b) with ASL 2.0 syntax	Felix Singer
2022-12-12	soc/intel/acpi: Replace Add(a,b,c) with ASL 2.0 syntax	Felix Singer
2022-02-25	arch/x86: consolidate HPET base address definitions	Felix Held
2020-08-05	{sb,soc}/intel/*/acpi/lpc.asl: Drop commented-out code	Angel Pons
2020-05-11	treewide: Remove "this file is part of" lines	Patrick Georgi
2020-04-06	soc/intel/braswell: Use SPDX for GPL-2.0-only files	Angel Pons
2020-03-18	soc: Remove copyright notices	Patrick Georgi
2019-11-04	sb/intel: Use defined CONFIG_HPET_ADDRESS	Elyes HAOUAS
2019-07-10	soc/intel/braswell/acpi/lpc.asl: Allocate used ROM size only	Frans Hendriks
2019-03-08	coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)	Julius Werner
2018-11-28	src/soc/intel/braswell/acpi/lpc.asl: Add ACPI and GPIO bases	Frans Hendriks
2018-11-21	soc/intel/braswell: Disable OS use of HPET	Frans Hendriks
2018-07-29	soc/intel: Remove legacy static TPM asl code	Philipp Deppenwiese
2017-11-30	acpi/tpm: remove non-existent IRQ for Infineon TPM chip	Matt DeVillier
2017-11-30	acpi/tpm: update TPM preprocessor guards	Matt DeVillier
2015-10-31	tree: drop last paragraph of GPL copyright header	Patrick Georgi
2015-06-25	Braswell: Add Braswell SOC support	Lee Leahy
2015-05-28	Remove address from GPLv2 headers	Patrick Georgi
2015-05-23	Braswell: Use Baytrail as Comparison Base	Lee Leahy