| Age | Commit message (Expand) | Author |
|---|---|---|
| 2020-03-18 | soc: Remove copyright notices | Patrick Georgi |
| 2019-11-04 | sb/intel: Use defined CONFIG_HPET_ADDRESS | Elyes HAOUAS |
| 2019-07-10 | soc/intel/braswell/acpi/lpc.asl: Allocate used ROM size only | Frans Hendriks |
| 2019-03-08 | coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX) | Julius Werner |
| 2018-11-28 | src/soc/intel/braswell/acpi/lpc.asl: Add ACPI and GPIO bases | Frans Hendriks |
| 2018-11-21 | soc/intel/braswell: Disable OS use of HPET | Frans Hendriks |
| 2018-07-29 | soc/intel: Remove legacy static TPM asl code | Philipp Deppenwiese |
| 2017-11-30 | acpi/tpm: remove non-existent IRQ for Infineon TPM chip | Matt DeVillier |
| 2017-11-30 | acpi/tpm: update TPM preprocessor guards | Matt DeVillier |
| 2015-10-31 | tree: drop last paragraph of GPL copyright header | Patrick Georgi |
| 2015-06-25 | Braswell: Add Braswell SOC support | Lee Leahy |
| 2015-05-28 | Remove address from GPLv2 headers | Patrick Georgi |
| 2015-05-23 | Braswell: Use Baytrail as Comparison Base | Lee Leahy |
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index : coreboot.git | |
| my copy of coreboot | User & |
| summaryrefslogtreecommitdiff |