coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2020-05-01	soc/intel/baytrail: Fix 16-bit read/write PCI_COMMAND register	Elyes HAOUAS
2020-04-06	soc/intel/baytrail: Use SPDX for GPL-2.0-only files	Angel Pons
2020-03-18	soc: Remove copyright notices	Patrick Georgi
2020-03-03	soc/baytrail: hook up smmstore	Matt DeVillier
2019-12-19	src/soc/intel: Remove unused <stdlib.h>	Elyes HAOUAS
2019-11-27	soc/intel/baytrail: Don't reinitialize SPI after lockdown	Arthur Heymans
2019-11-09	ELOG: Introduce elog_gsmi variants	Kyösti Mälkki
2019-08-13	cpu/x86: Separate save_state struct headers	Kyösti Mälkki
2019-03-08	coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)	Julius Werner
2019-03-01	device/pci: Fix PCI accessor headers	Kyösti Mälkki
2018-12-05	elog: make elog's SMM handler code follow everything else	Patrick Georgi
2018-06-14	src: Use of device_t is deprecated	Elyes HAOUAS
2017-07-13	soc/intel: add IS_ENABLED() around Kconfig symbol references	Martin Roth
2016-07-15	soc/intel/baytrail: use common Intel ACPI hardware definitions	Aaron Durbin
2015-10-31	tree: drop last paragraph of GPL copyright header	Patrick Georgi
2015-05-21	Remove address from GPLv2 headers	Patrick Georgi
2015-04-10	baytrail: Switch from ACPI mode to PCI mode for legacy support	Marc Jones
2015-04-07	baytrail: Change all SoC headers to <soc/headername.h> system	Julius Werner
2015-04-06	baytrail: reinitialize spi controller in SMM finalization	Aaron Durbin
2014-12-08	intel/baytrail: Spelling fixes	Martin Roth
2014-12-02	Replace hlt with halt()	Patrick Georgi
2014-05-06	baytrail: add GPIO SMI support	Aaron Durbin
2014-02-16	baytrail: SMM support	Aaron Durbin