coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2020-09-21	src/soc/intel: Drop unneeded empty lines	Elyes HAOUAS
2020-07-26	{sb,soc}/intel/*/.c: Use macros for PCI COMMAND bits	Angel Pons
2020-06-30	ACPI: Drop typedef global_nvs_t	Kyösti Mälkki
2020-06-24	ACPI: Replace uses of CBMEM_ID_ACPI_GNVS	Kyösti Mälkki
2020-05-11	treewide: Remove "this file is part of" lines	Patrick Georgi
2020-05-01	soc/intel/baytrail: Fix 16-bit read/write PCI_COMMAND register	Elyes HAOUAS
2020-04-06	soc/intel/baytrail: Use SPDX for GPL-2.0-only files	Angel Pons
2020-03-18	soc: Remove copyright notices	Patrick Georgi
2018-12-19	soc: Remove useless include <device/pci_ids.h>	Elyes HAOUAS
2018-05-24	soc/intel/baytrail: Get rid of device_t	Elyes HAOUAS
2015-10-31	tree: drop last paragraph of GPL copyright header	Patrick Georgi
2015-05-21	Remove address from GPLv2 headers	Patrick Georgi
2015-04-07	baytrail: Change all SoC headers to <soc/headername.h> system	Julius Werner
2014-05-10	baytrail: utilize reg_script_run_on_dev()	Aaron Durbin
2014-05-10	baytrail: Add support for LPSS and SCC devices in ACPI mode	Duncan Laurie
2014-05-07	baytrail: initialize common SSC functionality	Aaron Durbin