index
:
coreboot.git
macbookair5_2
macbookpro10_1
main
master
mbp101_medisable
mbp101_medisable_1
mbp82
x230
my copy of coreboot
gitea
about
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
src
/
soc
/
intel
/
baytrail
/
romstage
/
romstage.c
Age
Commit message (
Expand
)
Author
2019-08-21
arch/x86: Rename some mainboard_romstage_entry()
Kyösti Mälkki
2019-08-21
intel/fsp1_0,baytrail,rangeley: Tidy up use of preprocessor
Kyösti Mälkki
2019-08-18
cpu/intel: Enter romstage without BIST
Kyösti Mälkki
2019-08-15
cpu/x86/smm: Promote smm_memory_map()
Kyösti Mälkki
2019-08-15
arch/x86: Add postcar_frame_common_mtrrs()
Kyösti Mälkki
2019-08-15
cpu/intel: Refactor platform_enter_postcar()
Kyösti Mälkki
2019-07-04
arch/x86: Adjust size of postcar stack
Kyösti Mälkki
2019-03-08
coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)
Julius Werner
2019-03-04
device/mmio.h: Add include file for MMIO ops
Kyösti Mälkki
2019-03-01
device/pci: Fix PCI accessor headers
Kyösti Mälkki
2019-02-13
soc/intel/baytrail: Don't use CAR_GLOBAL
Arthur Heymans
2019-02-12
postcar: Make more use of postcar_frame_add_romcache()
Nico Huber
2019-01-08
cpu/intel/car: Prepare for C_ENVIRONMENT_BOOTBLOCK
Kyösti Mälkki
2018-12-30
cpu/intel/car: Drop remains of setup_stack_and_mtrrs()
Kyösti Mälkki
2018-12-28
soc/intel: Drop romstage_after_car()
Kyösti Mälkki
2018-12-05
soc/intel/baytrail: Implement POSTCAR stage
Arthur Heymans
2018-12-05
soc/intel/baytrail: Use postcar_frame functions to set up frame
Arthur Heymans
2018-11-16
src: Remove unneeded include <cbfs.h>
Elyes HAOUAS
2018-10-22
intel: Use CF9 reset (part 1)
Patrick Rudolph
2018-10-08
src: Use tabs for indentation
Elyes HAOUAS
2018-07-25
drivers/tpm: Add TPM ramstage driver for devices without vboot.
Philipp Deppenwiese
2018-07-09
src/soc: Use "foo *bar" instead of "foo* bar"
Elyes HAOUAS
2018-06-04
security/tpm: Unify the coreboot TPM software stack
Philipp Deppenwiese
2018-04-26
src: Fix a typo on "mtrr"
Elyes HAOUAS
2018-01-18
security/tpm: Change TPM naming for different layers.
Philipp Deppenwiese
2018-01-18
security/tpm: Move tpm TSS and TSPI layer to security section
Philipp Deppenwiese
2017-10-04
chromeec: Remove checks for EC in RO
Daisuke Nojiri
2017-07-18
vboot: Remove get_sw_write_protect_state callback
Julius Werner
2017-07-13
soc/intel: add IS_ENABLED() around Kconfig symbol references
Martin Roth
2016-12-01
lib: put romstage_handoff implementation in own compilation unit
Aaron Durbin
2016-12-01
romstage_handoff: remove code duplication
Aaron Durbin
2016-11-18
intel post-car: Increase stacktop alignment
Kyösti Mälkki
2016-10-31
lib/prog_loaders: use common ramstage_cache_invalid()
Aaron Durbin
2016-07-31
src/soc: Capitalize CPU, ACPI, RAM and ROM
Elyes HAOUAS
2016-07-15
soc/intel/baytrail: use common Intel ACPI hardware definitions
Aaron Durbin
2016-07-10
intel post-car: Consolidate choose_top_of_stack()
Kyösti Mälkki
2016-06-29
intel romstage: Use run_ramstage()
Kyösti Mälkki
2016-06-22
Ignore RAMTOP for MTRRs
Kyösti Mälkki
2016-02-26
tree wide: Convert "if (CONFIG_.*_TPM.*)" to "if (IS_ENABLED(...))"
Denis 'GNUtoo' Carikli
2015-10-31
tree: drop last paragraph of GPL copyright header
Patrick Georgi
2015-10-15
cpu/mtrr.h: Fix macro names for MTRR registers
Alexandru Gagniuc
2015-09-24
coreboot: move TS_END_ROMSTAGE to one spot
Aaron Durbin
2015-09-23
chromeos: vboot and chromeos dependency removal for sw write protect state
Paul Kocialkowski
2015-06-09
cbmem: add indicator to hooks if cbmem is being recovered
Aaron Durbin
2015-06-09
cbmem: Unify CBMEM init tasks with CBMEM_INIT_HOOK() API
Kyösti Mälkki
2015-05-27
Move TPM code out of chromeos
Vladimir Serbinenko
2015-05-21
Remove address from GPLv2 headers
Patrick Georgi
2015-04-22
coreboot: common stage cache
Aaron Durbin
2015-04-07
baytrail: Change all SoC headers to <soc/headername.h> system
Julius Werner
2015-02-15
x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointer
Kevin Paul Herbert
2015-01-14
baytrail broadwell: Use timestamps internal stash
Kyösti Mälkki
2015-01-05
timestamps: Switch from tsc_t to uint64_t
Stefan Reinauer
2014-10-28
baytrail: romstage: Add function to check SW WP status for vboot
Shawn Nematbakhsh
2014-09-19
baytrail/rambi: spi, charger, and audio updates
Aaron Durbin
2014-07-08
soc: Trivial - drop trailing blank lines at EOF
Edward O'Callaghan
2014-05-13
baytrail: snapshot power state in romstage
Aaron Durbin
2014-05-10
baytrail: allow ramstage_cache_location() usage in ramstage
Aaron Durbin
2014-05-07
baytrail: enable caching and prefetching in spi controller
Aaron Durbin
2014-05-07
baytrail: ensure init_chromeos() is called in romstage
Aaron Durbin
2014-05-06
baytrail: add support for S3 resume
Aaron Durbin
2014-02-27
baytrail: increment boot count for elog
Aaron Durbin
2014-02-24
baytrail: initialize chromeos EC if present in romstage
Aaron Durbin
2014-02-16
baytrail: SMM support
Aaron Durbin
2014-02-15
coreboot: infrastructure for different ramstage loaders
Aaron Durbin
2014-02-13
baytrail: add vboot ramstage verification
Aaron Durbin
2014-02-11
baytrail: move early init to before mainboard
Aaron Durbin
2014-02-11
baytrail: set max frequency early in romstage
Aaron Durbin
2014-02-05
baytrail: initialize punit
Aaron Durbin
2014-02-05
baytrail: disable tco timer
Aaron Durbin
2014-02-05
baytrail: program PUNIT memory-mapped base address
Aaron Durbin
2014-02-05
baytrail: start collecting timestamps
Aaron Durbin
2014-01-31
baytrail: initialize graphics before MRC
Aaron Durbin
2014-01-31
baytrail: add initial support
Aaron Durbin