index
:
coreboot.git
macbookair5_2
macbookpro10_1
main
master
mbp101_medisable
mbp101_medisable_1
mbp82
x230
my copy of coreboot
gitea
about
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
src
/
soc
/
intel
/
baytrail
/
romstage
/
cache_as_ram.inc
Age
Commit message (
Expand
)
Author
2019-02-11
soc/intel/baytrail: Use non-evict CAR setup
Arthur Heymans
2019-01-23
soc/intel/baytrail/romstage: Remove unneeded white space
Elyes HAOUAS
2019-01-08
cpu/intel/car: Prepare for C_ENVIRONMENT_BOOTBLOCK
Kyösti Mälkki
2019-01-08
arch/x86: Unify bootblock MMX register usage
Kyösti Mälkki
2018-12-05
soc/intel/baytrail: Implement POSTCAR stage
Arthur Heymans
2018-12-05
soc/intel/baytrail: Improve CAR setup
Arthur Heymans
2018-10-11
src: Move common IA-32 MSRs to <cpu/x86/msr.h>
Elyes HAOUAS
2016-06-18
intel cache_as_ram: Fix typo in comment
Kyösti Mälkki
2016-06-17
Fix some cbmem.h includes
Kyösti Mälkki
2016-05-03
intel/baytrail: use fmap information for code caching
Patrick Georgi
2015-10-31
tree: drop last paragraph of GPL copyright header
Patrick Georgi
2015-10-15
cpu/mtrr.h: Fix macro names for MTRR registers
Alexandru Gagniuc
2015-07-07
x86: Drop -Wa,--divide
Stefan Reinauer
2015-06-08
Remove empty lines at end of file
Elyes HAOUAS
2015-05-21
Remove address from GPLv2 headers
Patrick Georgi
2014-10-19
x86 romstage: Move stack just below RAMTOP
Kyösti Mälkki
2014-02-11
baytrail: adjust cache policy during romstage
Aaron Durbin
2014-02-05
baytrail: start collecting timestamps
Aaron Durbin
2014-01-31
baytrail: add initial support
Aaron Durbin