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This patch removes all redundant reset code block from each SoC
and make use of common reset code block(fsp_reset.c) based on
SOC_INTEL_COMMON_FSP_RESET.
Respective SoC Kconfig to choose correct FSP global reset type as
per FSP integration guide.
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I71531f4cf7a40efa9ec55c48c2cb4fb6ea90531f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45337
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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This reverts commit 77cc3267fc970c710299a164ecbc471f9287d719.
Reason for revert: Breaks quark and also needs breaking down into multiple CLs as commented by Nico on CB:45541
Change-Id: Idf4ca74158df15483856754ee24cc4472a8e09b0
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44997
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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List of changes:
1. Rename do_global_reset() to force_global_reset()
2. Make force_global_reset() function static
3. Implement force_global_reset() into common/reset.c to avoid
dedicated SoC implementation
4. Remove redundant force_global_reset() implementation from
dedicated SoC
5. Make direct call to global_reset() from cse_lite.c
7. Drop CONFIG_HAVE_CF9_RESET_PREPARE Kconfig from APL SoC due
to common reset (soc/intel/common/reset.c) code migration
8. Remove unused function send_global_reset() from SKL me.c due
to common reset code migration
9. Delete heci.c from APL SoC as unused
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I1c5dc8d5606ef28ffaed4a64d90f470ae1ffc2a6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45541
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Stefan thinks they don't add value.
Command used:
sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool)
The exceptions are for:
- crossgcc (patch file)
- gcov (imported from gcc)
- elf.h (imported from GNU's libc)
- nvramtool (more complicated header)
The removed lines are:
- fmt.Fprintln(f, "/* This file is part of the coreboot project. */")
-# This file is part of a set of unofficial pre-commit hooks available
-/* This file is part of coreboot */
-# This file is part of msrtool.
-/* This file is part of msrtool. */
- * This file is part of ncurses, designed to be appended after curses.h.in
-/* This file is part of pgtblgen. */
- * This file is part of the coreboot project.
- /* This file is part of the coreboot project. */
-# This file is part of the coreboot project.
-# This file is part of the coreboot project.
-## This file is part of the coreboot project.
--- This file is part of the coreboot project.
-/* This file is part of the coreboot project */
-/* This file is part of the coreboot project. */
-;## This file is part of the coreboot project.
-# This file is part of the coreboot project. It originated in the
- * This file is part of the coreinfo project.
-## This file is part of the coreinfo project.
- * This file is part of the depthcharge project.
-/* This file is part of the depthcharge project. */
-/* This file is part of the ectool project. */
- * This file is part of the GNU C Library.
- * This file is part of the libpayload project.
-## This file is part of the libpayload project.
-/* This file is part of the Linux kernel. */
-## This file is part of the superiotool project.
-/* This file is part of the superiotool project */
-/* This file is part of uio_usbdebug */
Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Done with sed and God Lines. Only done for C-like code for now.
Change-Id: I3c6daa484a4aa133ff2ad79eb2b8efa159da3523
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40208
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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They're listed in AUTHORS and often incorrect anyway, for example:
- What's a "Copyright $year-present"?
- Which incarnation of Google (Inc, LLC, ...) is the current
copyright holder?
- People sometimes have their editor auto-add themselves to files even
though they only deleted stuff
- Or they let the editor automatically update the copyright year,
because why not?
- Who is the copyright holder "The coreboot project Authors"?
- Or "Generated Code"?
Sidestep all these issues by simply not putting these notices in
individual files, let's list all copyright holders in AUTHORS instead
and use the git history to deal with the rest.
Change-Id: I4c110f60b764c97fab2a29f6f04680196f156da5
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39610
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
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Make use of the common CF9 reset in SOC_INTEL_COMMON_RESET. Also
implement board_reset() as a "full reset" (aka. cold reset) as that
is what was used here for hard_reset().
Drop soc_reset_prepare() thereby, as it was only used for APL. Also,
move the global-reset logic.
We leave some comments to remind us that a system_reset() should
be enough, where a full_reset() is called now (to retain current
behaviour) and looks suspicious.
Note, as no global_reset() is implemented for Denverton-NS, we halt
there now instead of issuing a non-global reset. This seems safer;
a non-global reset might result in a reset loop.
Change-Id: I5e7025c3c9ea6ded18e72037412b60a1df31bd53
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/29169
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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With this patch apollolake uses the common PMC util
code.No regression observed on a APL platform.
Change-Id: I322a25a8b608d7fe98bec626c6696e723357a9d2
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/19375
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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There are many good reasons why we may want to run some sort of generic
callback before we're executing a reset. Unfortunateley, that is really
hard right now: code that wants to reset simply calls the hard_reset()
function (or one of its ill-differentiated cousins) which is directly
implemented by a myriad of different mainboards, northbridges, SoCs,
etc. More recent x86 SoCs have tried to solve the problem in their own
little corner of soc/intel/common, but it's really something that would
benefit all of coreboot.
This patch expands the concept onto all boards: hard_reset() and friends
get implemented in a generic location where they can run hooks before
calling the platform-specific implementation that is now called
do_hard_reset(). The existing Intel reset_prepare() gets generalized as
soc_reset_prepare() (and other hooks for arch, mainboard, etc. can now
easily be added later if necessary). We will also use this central point
to ensure all platforms flush their cache before reset, which is
generally useful for all cases where we're trying to persist information
in RAM across reboots (like the new persistent CBMEM console does).
Also remove cpu_reset() completely since it's not used anywhere and
doesn't seem very useful compared to the others.
Change-Id: I41b89ce4a923102f0748922496e1dd9bce8a610f
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/19789
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Fix the following errors and warning detected by checkpatch.pl:
ERROR: space required before the open parenthesis '('
ERROR: space prohibited before that close parenthesis ')'
ERROR: return is not a function, parentheses are not required
WARNING: space prohibited between function name and open parenthesis '('
TEST=Build for reef
Change-Id: I31f854adf3269ba6f77c4044fb3748bb1957841c
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18725
Tested-by: build bot (Jenkins)
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
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The following patch is based off of the UEFI 2.6 patch. The FSP header files
are temporarily staying in soc/intel/apollolake and FspUpd.h has been relocated
since the other headers expect it to be in the root of an includable directory.
Any struct defines were removed since they are defined in the headers and no
longer need to be explicity declared as struct with the UEFI 2.6 includes.
BUG=chrome-os-partner:54100
BRANCH=none
TEST=confirmed coreboot builds successfully
Change-Id: I10739dca1b6da3f15bd850adf06238f7c51508f7
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>#
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/16308
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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FSP 2.0 spec only defines 2 reset request (COLD, WARM) exit codes. The
rest 6 codes are platform-specific and may vary. Modify helper function
so that only basic resets are handled and let SoC deal with the rest.
Change-Id: Ib2f446e0449301407b135933a2088bcffc3ac32a
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/15730
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
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At first boot CSE spends long time preparing media for use. As result
it may not be able to deal with a CPU reset. Add reset_prepare()
callback that polls CSE readiness.
BUG=chrome-os-partner:55055
TEST=build with release version of fsp, reboot, observe polling for
CSE, then proper reboot happening
Change-Id: I639ef900b97132f1a7f269bb864d70009df9fdfe
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/15721
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Apollolake defines Global Reset where Host, TXE and PMC are reset.
During boot we may need to trigger a global reset as part of platform
initialization (or for error handling). Add functions to trigger
global reset, enable/disable it and lock global reset bit.
BUG=chrome-os-partner:54149
BRANCH=none
TEST=none
Change-Id: I84296cd1560a0740f33ef6b488f15f99d397998d
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/15198
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Looks like we need to do real cold reset in some FSP flows, so
reverting this.
This reverts commit 6f762171de4b8514fddd430052cbf24524e09e5d.
Change-Id: Ie948d264c4e2572dab26fdb9462905247a168177
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/15331
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
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Due to USB LDO issue in current steppings, cold reboot needs to be
temporarily disabled. Thus, hard_reset call should be the same as
soft_reset.
Once future steppings are available INTEL_COMMON_RESET can be enabled again.
Change-Id: If0ec56db3864d500acc93d2b363a78a6cd7632da
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15143
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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