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The ELOG for CSE updates was being added in fsp_params.c, but the
actual update happens in cse_lite.c. This commit moves the ELOG to
cse_lite.c to more accurately reflect where the event is happening.
This also removes the need for a sol_type variable in
meteorlake/romstage/fsp_params.c.
It also helps to avoid redundant ELOG event entry while performing
CSE update (due to CSE RO to RW switch dependency).
BUG=b:361253028 (Multiple CSE sync elog prints for Nissa/Trulo)
TEST=Able to see only one instance of ELOG while performimg CSE sync.
w/o this patch:
elogtool list
0 | Log area cleared | 4088
1 | Kernel Event | Clean Shutdown
2 | Early Sign of Life | MRC Early SOL Screen Shown
3 | Early Sign of Life | CSE Sync Early SOL Screen Shown
4 | System boot | 29
5 | Memory Cache Update | Normal | Success
6 | Early Sign of Life | CSE Sync Early SOL Screen Shown
w/ this patch:
elogtool list
0 | Log area cleared | 4088
1 | Early Sign of Life | MRC Early SOL Screen Shown
2 | Memory Cache Update | Normal | Success
3 | System boot | 30
4 | Memory Cache Update | Normal | Success
5 | Early Sign of Life | CSE Sync Early SOL Screen Shown
Change-Id: I37fe3f097e581f79bf67db1ceb923f10ce651d62
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84398
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Jakub Czapiga <czapiga@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
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Enable the CRASHLOG config option for Chrome OS boards. This allows the
Chrome OS crash reporter to collect and analyze crash dumps, aiding in
debugging and improving system stability.
TEST=Able to build and boot google/brox
Change-Id: Ia23ef1cbebdba9a3b724204eb25ee788afa3e8fd
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84365
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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When battery is disconnected and only adaptor is connected higher PL2
power draw causes cpu brown out and system does not boot to kernel. To
avoid this set Boot frequency UPD to 1. Reduce PL4 value to overcome
power spikes from SoC during boot. Remove Psys implementation as it
impacts active state platform performance.
BUG=b:335046538,b:329722827
BRANCH=None
TEST=Able to successfully boot on 3 different Brox proto2 SKU1
and SKU2 boards with 65W, 45W and 30W adaptors for 3
iterations of cold boot.
Change-Id: I58e136c607ea9290ecac0cee453d6632760a6433
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83752
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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With the release 20240910 of the Intel microcode repository, it also
includes the updated microcode file with version 0x129, which makes the
one from the coreboot blobs repo superfluous. Thus, use the one from the
Intel repository again.
Change-Id: I7fb58874719a8373072419e34b3f8923f7db927d
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84295
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ifbe76bd69d847603345a4a1fa4f41e529634fa92
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84158
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Should make the sorting order of the paths more obvious.
Change-Id: Ie73e717f37f80a11a903e99cc094ea4d76e1ca1f
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83827
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The Alder Lake "Client" FSP paths have been replaced by symlinks to
Raptor Lake in the FSP repo. Hence we get the same files anyway and
can spare us to maintain the individual paths.
Change-Id: Ia9b256ce1940894e2cf31acaa4a83ea39f6723b6
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83826
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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The `!FSP_USE_REPO` is most specific, if we're not using the FSP repo,
we can ignore all the FSP-repo paths. Hence put these first.
Having `FSP_TYPE_IOT` selected is also more specific, we can ignore all
the "Client" paths then. This makes sure that we don't catch a "Client"
by accident (otherwise we'd have to add a `!FSP_TYPE_IOT` for those).
Change-Id: Ibe9931d8f964a337c46fde31a3bc22c69d40eded
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83825
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
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Based on DOC #767454 (public) version 1.2. Allows to boot the
HARDKERNEL ODROID H4+ with N97 SoC. Without this patch the MCH ID
was not recognized and the SA driver did not pick up the stolen
ranges, causing the PCI MMIO allocation to be placed in the stolen
areas.
TEST=Boot HARDKERNEL ODROID H4+ with N97 SoC to Ubuntu 23.04.
Change-Id: I0fbdb12c6411e4109e68a13960b4570701629bc9
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84212
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Move the `BUILDING_WITH_DEBUG_FSP` Kconfig option from SoC-specific
files to the FSP2_0 driver Kconfig to avoid duplication. Also slightly
improves the option's prompt and help text.
TEST=Built and booted google/rex successfully.
Change-Id: I5c3dce59c396f6c1665a3ed1b8c1bb5df0f5a8d4
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84220
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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This patch adds a new Kconfig option `FSP_PUBLISH_MBP_HOB` to
control the creation of the ME_BIOS_PAYLOAD_HOB (MBP HOB) by FSP.
Disabling this option can improve boot time on platforms that
do not utilize the MBP HOB, such as ChromeOS devices.
The option is disabled by default on ChromeOS and enabled
by default on other platforms.
On ADL-P based platforms, this option is forced to be enabled
as ADL-P FSP relies on MBP HOB for ChipsetInit version for
ChipsetInit sync.
Removed SoC specific implementation of `FSP_PUBLISH_MBP_HOB` config
from MTL and TGL config file.
TEST=Tested on ADL-P and ADL-N platforms. Verified that MBP HOB is
created when `FSP_PUBLISH_MBP_HOB` is enabled and not created when
it is disabled.
Also verified that the system boots successfully in both cases.
Change-Id: I21da00259c0b9bcca6f545291a6259e9cce8d900
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84217
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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This patch refactors ITSS related SoC specific macros by consolidating
them into a common itss.h file. This improves code maintainability and
reduces redundancy as each SoC previously defined the same macros.
Specific changes include:
- Move SoC specific ITSS macros into intelblocks/itss.h.
- SoC code now includes intelblocks/itss.h instead of the SoC-local
soc/itss.h.
- Drop soc/itss.h from static ASL files.
- Delete soc/itss.h from all SoC locals except Apollo Lake and
Sky Lake.
TEST=Able to build and boot google/hatch, google/xol and google/karis.
Change-Id: I6461dc93b0d21bec5429075bc26435bae3754d74
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84183
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
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This patch removes the GPIO_IRQ_START and GPIO_IRQ_END definitions
from itss.h for Alder Lake, Cannon Lake, Elkhart Lake, Jasper Lake,
Meteor Lake and Tiger Lake. These definitions are no longer needed.
TEST=Able to build and boot google/xol and google/karis.
Change-Id: I60a08ba2c894fd1c1af6c6aef3ddc4a33ec63e76
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84182
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I5cd04972936c14d92295915fad65c7a45a8108d9
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84152
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <czapiga@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Previously, `early_graphics_stop()` was skipped unconditionally if
`CONFIG(SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE)` was enabled. This led
to overlapping screens when CSE sync was not triggered in ramstage,
as both the eSOL message and the firmware splash screen would be
displayed.
This change refactors the condition for calling `early_graphics_stop()`
to ensure it is only skipped if a CSE firmware update is actually
required *and* `CONFIG(SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE)` is set.
This allows eSOL to display its message during CSE sync, but tears
down early graphics programming in other cases to prevent overlapping
screens.
Additionally, this change ensures that `early_graphics_stop()` is the
last function called by the romstage to guarantee proper cleanup.
BUG=b:362895813
TEST=Able to boot google/tivviks_ufs without overlapping screens.
Change-Id: Idc01bfc8963d65fcb0441300e7c9267eaaefefb9
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84144
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Amanda Hwang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
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This updated microcode fixes the recent voltage issues on the Raptor
Lake S platform. Intel provided this specific microcode just as an
attachment [1]. Thus, we've uploaded it to our own blobs repository,
which is why the path is changed.
Microcode signature:
sig 0x000b0671, pf_mask 0x32, 2024-07-18, rev 0x0129
[1] https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/issues/81
Change-Id: I6d01e38476b0d3dc5281ea1d85bac87043d122dd
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84132
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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According to RDC#646929 Power Map, there are two expected values of
VccInAuxImonIccImax and the value has to align with HW design.
But in current code, vccin_aux_imon_iccmax is hard code to 27000 (27A),
hence, provide a config for projects modification.
BUG=b:330117043
BRANCH=firmware-nissa-15217.B
TEST=Modify the register and add a printk to output a debug message
to observe whether the value is changing as expected.
Change-Id: I0651f0eb8a5c32b27c524e43bbf6f2a184b95657
Signed-off-by: Simon Yang <simon1.yang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82682
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
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This patch eliminates the LPC_IOE_COMA_EN and LPC_IOE_COMB_EN IO enables
from the io_enables variable in the pch_early_iorange_init() function
because lpc_io_setup_comm_a_b() is intended to activate legacy COM
ports like COM-A (0x3F8 - 0x3FF) and COM_B (0x2F8 - 0x2FF).
These COM ports are being activated unconditionally, which is
undesirable for the Intel Alder Lake platform and causes traffic over
the IO bus.
As a result, this code is being removed and platforms that select
DRIVERS_UART_8250IO can activate legacy COM ports.
BUG=b:354066052
TEST=Able to boot google/redrix to the operating system and confirm
that there was no traffic over legacy COMs while being monitored
using the eSPI analyzer.
Change-Id: I7a6e38bd151f823d37c07ee89a800489122cc209
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84080
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch removes the SOC_INTEL_GFX_MBUS_JOIN configuration option.
Support for fast modeset joining has been added to the mainline i915
kernel driver (https://patchwork.freedesktop.org/series/130480/),
making this coreboot-specific workaround unnecessary.
BUG=b:291885733
TEST=Successful build and boot of google/marasov with single and dual
displays, no redundant boot splash.
Change-Id: I53c08a0e7a40b24db7cc910c5b9adc2376a9bb17
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84030
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paz Zcharya <pazz@google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
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Change-Id: I4fc824bef1daf8c12eb671c58de9019ce5a23a2e
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83575
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
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These field defines are SOC-specific. The AUX bias virtual wire field
positons are shifted in PTL.
In MTL SOC and older:
7:0 GROUP_ID Group ID in PCH GPIO
10:8 BIT_NUM Data bit Position in PCH GPIO
23:16 VW_INDEX VW Index in PCH GPIO
In PTL SOC:
15:0 GROUP_ID Group ID in PCH GPIO; targeted SB_PORTID
18:16 BIT_NUM Data bit Position in PCH GPIO
31:24 VW_INDEX VW Index in PCH GPIO
BUG=361048817
TEST=boot to OS and use iotools to read AUX Bias Ctrl register to
verify the group ID, bit number, and vw index.
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I0f9c895590465b2f539c91834cf331fcd7efa996
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83980
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
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This patch extends the eSOL implementation on Alder Lake to render text
messages during late CSE sync (from ramstage).
Currently, the eSOL is limited to the early boot phase (until romstage)
and only displays FSP-M memory training warnings or messages during
early CSE sync (at romstage).
Platforms like Nissa/Nirul and Trulo, which use CSE sync from ramstage,
cannot display any eSOL messages, resulting in a brief black screen
during CSE firmware updates.
This patch implements the following logic to scale eSOL for late CSE
sync (at ramstage) without recompiling eSOL code for ramstage:
1. During boot, check if the MRC cache is available. This indicates the
need for memory/DRAM training and triggers an eSOL message.
2. For CSE lite SKUs (applicable to CrOS), leverage the
`is_cse_fw_update_required` API to check if the current CSE RW
firmware version differs from the CBFS metadata file version.
If so, trigger an eSOL message indicating a CSE sync is required.
3. If either condition #1 and/or #2 is true, the AP firmware renders
an eSOL text message using LibGfxInit for the Alder Lake platform.
BUG=b:359814797
TEST=eSOL text messages are displayed during CSE sync and FSP updates.
tirwen-rev3 ~ # elogtool list
0 | ... | Log area cleared | 4088
1 | ... | Early Sign of Life | MRC Early SOL Screen Shown
1 | ... | Early Sign of Life | CSE Sync Early SOL Screen Shown
2 | ... | System boot | 197
3 | ... | Memory Cache Update | Normal | Success
4 | ... | System boot | 198
5 | ... | Firmware Splash Screen | Enabled
Change-Id: I1c7d4475ed5cf6888df1beebab0641ee4203b497
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83975
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
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This patch prevents the eSOL screen from being wiped out on Alder Lake
platforms that use late CSE sync (from ramstage). This allows the eSOL
text message to remain visible until ramstage.
Currently, the eSOL only functions during the early boot phase (until
romstage), so platforms like Nissa/Nirul and Trulo, which use CSE sync
from ramstage, cannot display any eSOL messages to the user.
A future patch will ensure the eSOL remains relevant for CSE sync in
ramstage, but this patch is necessary to avoid tearing down the IGD text
mode when exiting romstage.
BUG=b:359814797
TEST=eSOL text mode is not torn down when exiting romstage.
Change-Id: I81548b4057ab95ce3da0dbc69703977baf0581f1
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83974
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
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This patch replaces the SoC-specific config option
`SOC_INTEL_ALDERLAKE_DEBUG_CONSENT` with the generic
`SOC_INTEL_COMMON_DEBUG_CONSENT`.
Additionally, updates the FSP configuration to use the new generic
config option.
TEST=Able to build and boot google/redrix without any functional impact
while debugging.
Change-Id: I9a9c81b72d707f5ed2e1a53c139ee22be0e30068
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83957
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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The previous implementation incorrectly assumed that the presence of a
UFS device implied the availability of the ISH partition. This is not
always true, especially on Alder Lake platforms where ISH may be
enabled by default even without UFS.
This patch fixes the issue by directly checking for the presence of the
ISH device to determine if the ISH partition is available.
BUG=b:359440547
TEST=1. Able to dump the ISH version with UFS device:
```
tirwen-rev3 ~ # cbmem -c -1 | grep ISH
[DEBUG] ISH version: 5.4.2.7780
```
2. Able to dump the ISH version with eMMC device:
```
trulo-rev1 ~ # cbmem -c | grep ISH
[DEBUG] ISH version: 5.4.2.7780
```
Change-Id: I411e36606c0697f91050af40e0636f7c64810e95
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83898
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
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If a root port doesn't use a clock request pin, we shouldn't check if
this pin number, which defaults to 0 when not set, is already used. This
fixes the following spurious warning that was previously printed for
each external PCIe port which has the 'PCIE_RP_CLK_REQ_UNUSED' flag set
and didn't set 'clk_req' to some unused clock request pin number:
Found overlapped clkreq assignment on clk req 0
Tested on the cw-al-4l-v2.0 mainboard that uses an Alder Lake N100 SoC
which I'm currently porting coreboot to. Also changing this for Meteor
Lake, since they have the same implementation in their romstage
fsp_params.c file
Change-Id: I3ee66ca5ed5a2d06dfb68c45a50e11eb2b93daa0
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83865
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
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This patch updates the early libgfx init config
(MAINBOARD_HAS_EARLY_LIBGFXINIT) used for Alder Lake SoC with a
generic CrOS/ChromeOS early sign of life config (CHROMEOS_ENABLE_ESOL)
This patch does not change the binary or the system behaviour and is
only meant to bind the early GFX initialization with a generic eSOL
config.
BUG=b:352651132
TEST=Able to build google/tivviks and checked the config in output
Change-Id: Ibc1b9190ac0e4d25f3c5517d74c9b519bc3bb349
Signed-off-by: Jayvik Desai <jayvik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83841
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Clock Power Management, ASPM and L1 Substates have been
configured the same way since Skylake. The main control to
enable or disable is Kconfig, and then the level can be overridden
in devicetree.
Despite the UPDs remaining the same since Skylake, this is not the
case for Alder Lake, Raptor Lake and Meteor Lake.
Taking `starlabs/starbook` as an example, at the time of this
commit it has PCIEXP_CLK_PM, PCIEXP_ASPM and PCIEXP_L1_SUB_STATE
enabled.
On Comet Lake, this results in the correct configuration, verified
with the lspci command:
```
LnkCap: Port #0, Speed 5GT/s, Width x1, ASPM L1, Exit Latency L1 <8us
ClockPM+ Surprise- LLActRep- BwNot- ASPMOptComp+
LnkCtl: ASPM L1 Enabled; RCB 64 bytes, Disabled- CommClk+
ExtSynch- ClockPM+ AutWidDis- BWInt- AutBWInt-
```
On Raptor Lake:
```
LnkCap: Port #0, Speed 16GT/s, Width x4, ASPM L1, Exit Latency L1 <64us
ClockPM- Surprise- LLActRep- BwNot- ASPMOptComp+
LnkCtl: ASPM Disabled; RCB 64 bytes, Disabled- CommClk+
```
Clock Power Management, ASPM and L1 Substates are also not configured
for CPU root ports.
Add helper functions to configure these correctly based on Kconfig, but
retain the capability to override the specific levels from devicetree.
Change-Id: I9db18859f9a04ad4b7c0c3f7992b09e0f9484a81
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81638
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
During the stages which use Cache-as-RAM (CAR), coreboot needs more than
1 KiB as configured in DCACHE_BSP_STACK_SIZE. After studying the UPDs
for various SoCs(ADL-P, ADL-N, RPL), coreboot stack requirement is
estimated to be 32 KiB. Update DCACHE_BSP_STACK_SIZE accordingly.
BUG=None
TEST=Build Brox BIOS image and boot to OS.
Change-Id: I723ba1f4289c393fe7376f989d760b26e75b33da
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83680
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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|
This reverts commit 59ee65d271c7c617bcc240019231da4f0bd04db6.
Reason for revert:
- Usb4CmMode & CnviWifiCore Upds are available starting with TWL FSP
version v5222.01. Therefore, no special handling is required.
BUG=b:330654700
TEST=Able to build google/tivviks.
Change-Id: I3c74ec5b9924e88a26984fe8d3275ba80edb14ab
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83658
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
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Add definition of the IOM_READY bit in the IOM_TYPEC_STATUS_1
register. Needed by Protectli VP66XX boards to poll for this bit
for about 2 seconds before FSP Silicon Init to have USB functionality.
ME is supposed to start fetching and executing the TCSS IPs FW right
after DRAM Init Done message, which happens after MRC. For most
platforms the time interval between the end of MemoryInit and start of
SiliconInit is enough for IOM_READY to get set.
TEST=Poll the IOM_READY bit on VP66XX platform and observe the
TCSS XHCI is up in lspci.
Change-Id: If868a77852468ebb73526b1571191cbdeb1804b9
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83356
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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|
This patch updates Alder Lake code to use the common eSPI header file
(`intelpch/espi.h`) instead of the SoC-specific one.
BUG=none
TEST=Builds successfully for google/redrix.
Change-Id: Ib4452547325042de48ee4fca3d3910a031b56b64
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83484
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Replace the SoC-specific `report_cache_info()` function with the
common `car_report_cache_info()` API from `car_lib`. This promotes code
reuse and reduces SoC-specific implementation for cache reporting.
BUG=none
TEST=Builds and boots successfully on google/marasov platform.
Change-Id: I18be2c33dbe5186643af52823eb2fb185a296909
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83481
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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|
Issue: System hang occurred due to unhandled SPI synchronous SMI,
triggered by LOCK_ENABLE bit and WPD assertion.
Solution: Enabled SOC_INTEL_COMMON_BLOCK_SMM_TCO_ENABLE configuration
to allow the system to handle and clear SPI synchronous SMI.
BUG=b:350623902
TEST=reboot test on 40 google/xol by ODM, all passed w/o
hang.
Change-Id: I4c14b1e3d537e46e671e950c91c9d0042fe26836
Signed-off-by: Jamie Chen <jamie.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83432
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: SH Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-by: Edward Doan <edoan@chromium.org>
|
|
This patch extends the crashlog IP support beyond 32-bit mode to
support Intel future generation SoCs, which may require crashlog
support for 64-bit architectures. uintptr_t data type is used for
Address pointers and void* for dereferencing
BUG=b:346676856
TEST=Successfully built Meteor Lake (rex) and tested for google/rex0
and google/rex64 images.
Change-Id: I552257d3770abb409e2dcd8a13392506b5e7feb7
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83106
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
For most of SoCs, DRHD is by default with the size of 4KB. However,
larger sizes are allowed as well. Rename acpi_create_dmar_drhd to
acpi_create_dmar_drhd_4k to support the default case while a later
patch will re-add acpi_create_dmar_drhd with a size parameter.
TEST=intel/archercity CRB
Change-Id: Ic0a0618aa8e46d3fec2ceac7a91742122993df91
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83202
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
This change also drops a duplicated config default line, which might be
why this was omitted.
Change-Id: I2b4c8b316adaadec3e49d5162b37b37629331b06
Signed-off-by: Benjamin Doron <benjamin.doron@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83086
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This patch eliminates coreboot from loading microcode from RW CBFS
(when the RO descriptor is locked, which indicates a fixed RO image)
because the kernel can already patch the microcode on BSPs and APs
while booting to OS.
This may be a chance to lower the burden on the AP FW side because
patching microcode on in-field devices is subject to firmware updates,
which are rarely published and, if required, must go through the
firmware qualification testing procedure (which is costly, unlike
kernel updates for ucode updates).
1. The FIT loads the necessary microcode from the RO during reset.
2. Reloading microcode from RW CBFS impacts boot time
(~60ms, core-dependent).
3. The kernel can still load microcode updates.
ChromeOS devices leverage RO+RW-A/RW-B booting. The RO's microcode is
sufficient for initial boot, and the kernel can apply updates later.
BUG=none
TEST=Verified boot optimization; in-field devices skip RW-CBFS microcode
loading when RO is locked.
Change-Id: I68953d45d3624aba0a3be28bc7b266b7621ddcc4
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82999
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The UsbTcPortEn UPD for FSP-S is being set in ramstage, however the
equivalent FSP-M UPD, the UsbTcPortEnPreMem, was not being set.
Following the Meteor Lake example, set the UsbTcPortEnPreMem UPD
as well for Alder Lake.
Setting this FSP-M UPD will cause FSP to properly program sideband
use BSSB_LSx pins for the enabled Type-C ports. Required for proper
DCI debug and TCSS initialization flow.
Change-Id: If3b79167ec1769ddfb7d28a6c78a3e80bd10afe7
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80500
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
|
|
This patch introduces support for storing the MRC cache based on the
MRC version for both ADL-N and TWL platforms. It select the
MRC_CACHE_USING_MRC_VERSION option when client SOC_INTEL_ALDERLAKE_PCH_N
is chosen.
BUG=b:296433836
Change-Id: Icc7e4ecd84a7d2818d54acc6ac5d0592544bb9ce
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81038
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Brandon Weeks <bweeks@google.com>
|
|
This patch is to switch Client ADL-N FSP headers to vendorcode from IOT
headers. Also guard IOT headers & bin path with FSP_TYPE_IOT Kconfig.
BUG=b:296433836
TEST=Able to build and boot google/nivviks
Change-Id: I1ffcc3f284c213ff0533de3a0e228aacf523b380
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82781
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
PchPcieClockGating & PchPciePowerGating UPDs are not available for ADL_N
FSP headers. Add guard to Avoid PchPcieClockGating & PchPciePowerGating
programming for ADL_N FSP.
Change-Id: I2f1625038896b07c354498fe431cad97fb9b5bdb
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82917
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
|
|
Currently EOP message is sent to CSE late in the boot flow. Instead send
it asynchronously to save ~10 ms in boot time.
BUG=b:337330958
TEST=Build Brox BIOS Image and boot to OS.
Change-Id: I229d16a5dcd072958db3f59a9c364bf7508b3047
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82236
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
|
|
Alderlake and Raptorlake SoCs support DDR4 and DDR5, which have a total
SPD size of 512 bytes. Set this as the default and remove the setting
from mainboard Kconfigs.
Change-Id: I8703ec25454a0cd55a3de70f73d2117285a833ae
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82115
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add the graphics device IDs for Twinlake platform based on
Platform External Design Specification.
Document ID: 645548
BUG=b:326901448
TEST=Build tivviks and verify the IGD IDs.
Change-Id: Ide008d5c5302bd589784bc917a2610c42a0fdee4
Signed-off-by: Sowmya V <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82038
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
|
|
Change-Id: Ic690a7543f8a1e072650917d7a1e9e3b9dc371a3
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81823
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jakub Czapiga <czapiga@google.com>
|
|
IoT variants of the RaptorLake FSP support the `PchPciePowerGating` and
`PchPcieClockGating` UPDs, so, remove the preprocessor check that only
enabled it for AlderLake FSPs.
Change-Id: I583a4b257b72f992fdb6390d00e187d04a749177
Signed-off-by: Benjamin Doron <benjamin.doron@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81803
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
|
|
Change-Id: I93e6989633b9ac1b2738b812e3f8b442ecfdcbf0
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81813
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: I265e427254ce9f735e65b0631c43f98bc778a34f
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81812
Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
|
|
The RPL FSP currently uses HECI commands to retrieve the chipset
initialization version because the MBP HOB creation is disabled
(SkipMbpHob=1). This has resulted in an approximate 150ms increase in
boot time. Investigations are ongoing to determine the cause of the
delay when using HECI commands. As an interim solution, this patch sets
SkipMbpHob=0, enabling the use of MBP HOB or acquiring the chipset
initialization version, which is expected to reduce the boot time.
BUG=b:328430167
TEST= Able to build,boot and collect boot time data of brya.
With this patch:
963:returning from FspMultiPhaseSiInit 1,337,481 (249,046)
Without this patch:
963:returning from FspMultiPhaseSiInit 1,496,268 (408,194)
Signed-off-by: Kilari Raasi <kilari.raasi@intel.com>
Change-Id: I8a99a57b644732074e41051d99e63576f1edd229
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81446
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
|
|
Change-Id: I79b93b0ca446411e2a1feb65d00045e3be85ee8a
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81489
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
|
|
This patch adds timestamp start/end entries around the eSOL
implementation to track the panel initialization time while rendering
the eSOL screen.
TEST=Able to build and boot google/omnigul.
555: started early sign-off life (eSOL) notification 643,694 (40)
556: finished early sign-off life (eSOL) notification 1,072,143 (428,449)
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I51c04fc4bd2540b3f42e2f896178521d297ef246
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81387
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
|
|
ADL-N FSP uses 202111 Edk2. select UDK_202111_BINDING Kconfig for ADL-N
SoC.
BUG=b:296433836
TEST=Able to build and boot google/crassk.
Change-Id: If277ede4307515035389cd0e9d34c15cc80f278c
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80274
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Adds config-based guards for Usb4CmMode and CnviWifiCore UPDs, specific
to Twin Lake SoCs (SOC_INTEL_TWINLAKE).
Prevents compilation errors due to missing UPD definitions.
BUG=b:330654700
TEST=Able to build google/tivviks.
Change-Id: I6e0a9a7536df6295e23bf06003539e56bb98a311
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81376
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add System Agent IDs for Raptor Lake SKUs based on RPL Datasheet
(Doc ID: 743844) & EDS Vol 1 (Doc ID: 640555).
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: I805040c65852742f1bbc43b443e115bcb0a930aa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81115
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The CnviWifiCore UPD exists for ADL (version 4263) and RPL
(version 4415). Remove the guard so it is set correctly.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I9943ee43a442a43d75e78d1551e46dcea39db357
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81079
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The `platform_fsp_multi_phase_init_cb' callback is specific to FSP-S,
let's rename it 'platform_fsp_silicon_multi_phase_init_cb' to avoid
any confusion.
Change-Id: I86b69e2069f08023e6f48464f6df4593710aa9ee
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81094
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
Mainboards using Intel Twin Lake (TWL) SoC shall select
SOC_INTEL_TWINLAKE.
BUG=none
BRANCH=firmware-nissa-15217.B
TEST=Build and boot Google/Yaviks with Twin Lake kconfig enabled
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: Ie4c5d137ee54512313344f853e7ca66d1fd25003
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80688
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
System sleep time (SLP_S0 signal asserted) is measured in ticks, for
Alder Lake soc in 122us (i.e. ~8197Hz) granularity/ticks.
BUG=b:301854636
TEST=/sys/devices/system/cpu/cpuidle/
low_power_idle_system_residency_us" will show system idle residency time
Change-Id: I449f7ed0d9ef891ae5266e8fd784a063a75e38eb
Signed-off-by: Marx Wang <marx.wang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80665
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
ADL-M is not commercially available, so it can be removed.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: If769989f7a0434e32ebbcc8eac9b965b70ca71ed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80614
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
|
|
The ACPI is adjusted based on SOFTWARE_CONNECTION_MANAGER, so set
the UPD to match this to avoid the connection type being mismatched.
If it's mismatched, the TBT port will time out.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I8a99db165301ce08caf55aac0e33ca1994559d62
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80486
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
|
|
This patch adds support for using ADL N 4-core MCH ID 0x4618.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I7b9fc64ccf8e2401dcd55607e8f09b348efb3182
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80166
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This patch adds support for using ADL N 4-core MCH ID 0x4618.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I3e4855ce93666c54ab35def9b58e4b13bc9a8672
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80488
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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This is now generated by acpigen in the common/block/sata module.
Change-Id: Ic45a059f47a090aa1993e83884408a82826b30cf
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80562
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Change-Id: Ie7bc4f3ae00bb9601001dbb71e7c3c84fd4f759a
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80596
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Improves code maintainability and potentially reduces redundancy by
using the IA common implementation.
Additionally, drop the unused macros from SoC local.
TEST=Build and boot successful on google/marasov.
Change-Id: I290fea99f04cfc9f18e5f1435ed07de42995869f
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80403
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Leverages common SA header definitions for Host Bridge registers.
Renames DSM_BASE_ADDR_REG to BDSM and DPR_REG to DPR for brevity.
Additionally, made some minor code alignment corrections while
adding newer macros in the header file.
TEST= Build and boot successful on google/screebo.
Change-Id: I476f213d75a0978336b3749a5ba1499107eb2238
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80361
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: sridhar siricilla <siricillasridhar@gmail.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
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Macros can be confusing on their own; hiding commas make things worse.
This can sometimes be downright misleading. A "good" example would be
the code in soc/intel/xeon_sp/spr/chip.c:
CHIP_NAME("Intel SapphireRapids-SP").enable_dev = chip_enable_dev,
This appears as CHIP_NAME() being some struct when in fact these are
defining 2 separate members of the same struct.
It was decided to remove this macro altogether, as it does not do
anything special and incurs a maintenance burden.
Change-Id: Iaed6dfb144bddcf5c43634b0c955c19afce388f0
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80239
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Jakub Czapiga <czapiga@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
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The .inc suffix is confusing to various tools as it's not specific to
Makefiles. This means that editors don't recognize the files, and don't
open them with highlighting and any other specific editor functionality.
This issue is also seen in the release notes generation script where
Makefiles get renamed before running cloc.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ib479b93b7d0b2e790d0495b6a6b4b4298a515d9a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80073
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This reverts commit acbc4912375085a099c2427def464d6e481f2a90.
Reason for revert: CB:79525 fixes the issue that led to the revert
by not maintaining the heap in the SMM-stored copy of ramstage at all.
Change-Id: I3c8ef785486d275c9341859d34fce12253bd2bb9
Signed-off-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80023
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Make it possible to enable C1e from the devicetree by adding
`c1e_enable`. C1e was disabled by ea2a38be323173075db3b13729a4006ea1fef72d
for all RPL SOCs to reduce noise.
This will ensure that boards that disabled it based on CPUID are unchanged.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I758621393cb39345c2ba7b19a32872e84e1c5a19
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77088
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Move the existing FSP 4301.01 headers for Raptor Lake out of
subdirectory called 43101.01 to follow standard process.
Change-Id: I710f373acd37e9e0f8b50084a1a7e9fbda816e8c
Signed-off-by: Kulkarni, Srinivas <srinivas.kulkarni@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79475
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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This patch ensures that the LidStatus UPD is passed a dynamic value,
rather than always passing 1 (CONFIG_RUN_FSP_GOP enabled) for FSP 2.0
devices.
Problem statement:
* FSP-S GFX PEIM initializes the on-board display (eDP) even when the
LID is physically closed, because LidStatus is always set to 1.
* FSP-S skips external display initialization even when the LID is
closed.
Solution:
* FSP-S GFX PEIM module understands the presence of an external display
if LidStatus is not set, and tries to probe the other display
endpoint.
* Statically passing LidStatus as always enabled (aka 1) does not
illustrate the exact device scenarios, so this patch updates
LidStatus dynamically by reading the EC memory map offset.
BUG=b:313886118
TEST=Able to build and boot google/marasov to redirect the display
using external HDMI monitor while LID is closed.
Change-Id: Idb1d71bd54837630f36d43a45effc53d35f9cb70
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79352
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The Client FSP for Raptor Lake-S is present on the Intel FSP repository,
so there is no need to restrict Raptor Lake-S FSP binary repository to
IoT only.
TEST=Build and boot MSI PRO Z790-P
Change-Id: I77aecd6e2d753732bf6358afe2c7ea0491348387
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78411
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-by: Eric Lai <ericllai@google.com>
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The combination of SOC_INTEL_RAPTORLAKE_PCH_S and FSP_TYPE_IOT is
currently broken. By default, e.g. for MSI PRO Z790-P, the
FSP_HEADER_PATH does not match the default FSP_FD_PATH. For headers
the client FSP is selected, while for the FD file, IoT FSP binary
is chosen. The order of default for both headers and FD file must be
the same to match the headers and binaries.
TEST=Build default MSI PRO Z790-P config and see that FSP_HEADER_PATH
matches FSP_FD_PATH FSP variant-wise.
Change-Id: I8db5ea10c2986ff8d3fa7d616b3f1617d05f0260
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78410
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This reverts commit 44a48ce7a46c36df69f7b2cf3552bf10fa5f61b6.
Reason for revert: It breaks wakeup from suspend on a bunch of boards.
While this approach of eyeballing "correct" values by chipset _should_
be fixed, it should also be accompanied by compile time verification
that the memory map works out.
Since nobody seems to care enough, let's just revert this, instead of
keeping the tree broken for a bunch of configurations.
Change-Id: I3cd73b6ce8b15f06d3480a03ab472dcd444d7ccc
Signed-off-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78850
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Add an entry in the min_pci_sleep_states array for SA_DEVFN_DPTF,
to correct warning in cbmem log:
[WARN] unknown min d_state for PCI device 00:04.0
TEST=build/boot google/brya (banshee), verify warning not present in
cbmem log, verify entry for DPTF device in ACPI LPI constraint list.
Change-Id: I2a9976b065f08e4acd31c3deca13c5278f031a90
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78877
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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Thanks to x86 CBFS cache support, we can leverage cbfs_map() function
to load the VBT binary regardless of if it is compressed or not.
Change-Id: I1e37e718a71bd85b0d7dee1efc4c0391798f16f7
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77886
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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The ACPI name of any device needs to match the name used for generating
the S0i3 LPI constraint list, which comes from soc_acpi_name() for each
SoC. The names used for the eMMC controller do not match, which will
lead to broken ACPI tables since the LPI constriant will reference
an ACPI device which does not exist. Some OSes tolerate this better
than others, but it should still be corrected.
TEST=build/boot google/{hatch,volteer, brya}, dump ACPI and verify
no invalid device names referenced.
Change-Id: Icbc22b6b2a84bbe73f1b09083f27081612db5eba
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78825
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
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On all targets the domain works as a host bridge. Xeon-sp code intends
to feature multiple host bridges below a domain, hence rename the
function to pci_host_bridge_scan_bus.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I4e65fdbaf0b42c5f4f62297a60d818d299d76f73
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78326
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
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The microcode for RPL-S C0 and H0 is actually available, however, the
name of the file contained a typo: 06-b7-05 vs 06-bf-05. Fix the typos
in the comments.
Moreover, the ADL-S C0/H0 microcode file 06-97-05 has the same sha256
sum as the equivalent RPL-S C0/H0 microcode file 06-bf-05. The sha256
sum of ADL-S/RPL-S C0/H0 microcode on intel-microcode tag
microcode-20230808:
5d8d4a4d5456c43b7cc04937c80aec094ccbf3bd89f34ffa5182913ef944a9f9
Update the comments to correctly indicate supported CPU steppings.
Change-Id: I4c848e0dfc40f6c8e26a9b31e7c4cf4c5a09128f
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78413
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Remove the existing FSP 4221.00 headers subdirectory called
4221.00_google, and have Google vendor devices use FSP 4301.01.
BUG=b:306181828
TEST=`emerge-brya coreboot chromeos-bootimage`, flash and boot skolas to kernel.
Change-Id: Ic64b3aec62f0d6302278393bf06d090f43c0d592
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78444
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: <srinivas.kulkarni@intel.com>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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This patch ensures that the IGD joins the MBUS when the firmware splash
screen feature is enabled (aka BMP_LOGO config is enabled).
For ChromeOS platform, it prevents the i915 driver from reinitializing
the display, which can save up to 75ms-80ms of boot time and eliminate
a brief period of blank screen between the firmware splash screen and
the OS login prompt.
BUG=b:284799726
TEST=Able to build and boot google/rex.
Change-Id: I36af167afa902053a987602d494a8830ad9b1b1a
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78387
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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For Raptor Lake, select Raptor Lake's .fd file and header.
TEST=Boot to OS on Google Brya board with RPL silicon.
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: Ib3172b06b23e19be453142af764dd027bfe8043d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78014
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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We have a tiny HEAP_SIZE by default, except when we don't, and
mainboards that override it, or not.
Since memory isn't exactly at a premium these days, and unused heap
doesn't cost anything extra, just crank it up to the highest value
we have in the tree by default and remove all overrides.
Change-Id: I918a6c58c02496e8074e5fba06e38d9cfd691020
Signed-off-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78270
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Intel GFX IP TRANS_DDI_FUNC_CTL register bit definitions have changed
since Tiger Lake.
This register is used to map ports and pipes to display controllers,
so reflecting the correct status is important for detecting physical
display end point devices.
This patch ensures that ADL, MTL, and TGL SoCs choose GMA version 2 to
properly reflect the updated port and pipe register definitions.
BUG=b:299137940
TEST=Build and boot google/rex successfully.
Change-Id: Ie2082747d18a5f136f410b1019be4d6c801617b1
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78079
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
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The ACPI methods for enabling USB wake are identical on ADL, CNL and
SKL. Move them to a common ASL file so they can be reused more easily
on other SoCs.
Also move the USB_PORT_WAKE_ENABLE macro used to create enable bitmasks
in devicetree to a common header.
BUG=b:300844110
TEST=Use abuild to build kinox, puff, and fizz with and without this
change. Check the generated dsdt.aml is unchanged.
Change-Id: Iabdfe2bece7fafc284ddf04382f1bbcacc370cce
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78085
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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Now that Intel has publicly released FSP headers/binaries for
RaptorLake-P/S client platforms, set the defaults accordingly if
FSP_USE_REPO is not selected. This does not change any existing
defaults as the RaptorLake headers in vendorcode are only used when
FSP_USE_REPO is not set.
TEST=build/boot google/brya (osiris)
Change-Id: Ida92d269fcaf6f323599ec174f4dcedbbe65f03c
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78190
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
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This patch selects LZ4 decompression for logo CBFS file. Able to save
2ms of the boot time when HAVE_FSP_LOGO_SUPPORT config is enabled.
However, the compressed BMP logo size is increased by ~2KB.
Raw BMP Image size is ~97KB.
BUG=b:284799726
TEST=Able to see pre-boot splash screen while booting google/redrix
with 32MB (W25Q256JWEIM) SPI-Flash.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I98e2c9a4f77d0b91f84eda9aec5060b236bd5e94
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78121
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Rather than disabling C State demotions for every single Raptor
Lake board due to an issue with S0ix, regardless of if they even
use S0ix, configure it in the mainboard.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I4f941a549bc717ae2f8ec961ead7ac7668347c99
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77087
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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Hook up the OC watchdog common block and initialize it if requested.
TEST=Enable watchdog on MSI PRO Z690-A and see the platform resets
after some time. Enable the watchdog in driverless mode and see the
platform no longer resets and periodic SMI keeps feeding the watchdog.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I1c2c640d48b7e03ad8cd8d6cdf6aac447e93cd86
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68945
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Added Raptor Lake U graphics device ids.
Renamed Raptor Lake U graphics device ids that were marked as
Raptor Lake P.
Added Raptor Lake P graphics device ids.
References:
RaptorLake External Design Specification Volume 1 (640555)
TEST=Boot to OS
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I44734f927764f872b89e3805a47d16c1ffa28865
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77898
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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DRIVERS_INTEL_MIPI_SUPPORTS_PRE_PRODUCTION_SOC is added to mipi camera
driver to extend the same support for all SoCs, so removing this config
from Alderlake SoC code.
BUG=None
TEST=Build rex and brya to check if the build passes without an
error.
Change-Id: I5bc23fce89f0ae22b64b90cb12621320cac30d85
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77859
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
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Move the existing FSP 4221.00 headers for Raptor Lake to a
subdirectory called 4221.00_google, and select this if the
vendor is Google.
Add the standard FSP 4301.01 headers to a separate directory,
from Intel download #686654, and select this for all other
vendors.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Icd99bdee1eeac70dfcaca3d07150d3de6bb83d81
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77101
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The ACPI used for Tiger Lake, Alder Lake and Meteor Lake are very
similar, so can be moved to shared code.
This commit aligns minor difference between then, such as comments and
tabs/spaces.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: If6554c7ef9e83740d7ec5dcca6a9d7e32fb182db
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77453
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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It makes the detection of this feature accessible without the
CONFIG_SOC_INTEL_COMMON_BLOCK_CPU dependency.
BUG=288978352
TEST=compilation
Change-Id: I005c4953648ac9a90af23818b251efbfd2c04043
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77697
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I57b54653bd29a728825210403c8f426eb1c9cc48
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75633
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
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Add SA_DEV_SLOT_GNA definition to SoCs missing it, so the name
resolves properly.
TEST=tested with rest of patch train
Change-Id: I31c8b14e5083fc8e212a4e32330125fa72696c73
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Signed-off-by: CoolStar <coolstarorganization@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77576
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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The RPL PCH uses a different ACPI Device ID than ADL PCH.
Ref: Intel 700 Series Chipset Family PCH Datasheet, Volume 1 (#743835)
Change-Id: I03f47a43ff985213ad617e834db7f974f687d877
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77150
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Similar situation happened last year when IoT FSP for ADL-S came out
before the Client FSP variant: https://github.com/intel/FSP/issues/83
It seems IoT FSP publishes the MemInfoHob.h file much later due to
legal reasons. Hack the missing file to get the builds using RPL-S IoT
FSP from repo working properly.
This change could be merged, subject for later revert (when the header
file is published).
Change-Id: Iec35db4573a3c3d011e4c1edf1c82a5c34438695
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76324
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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