coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2020-12-04	src/soc/intel/alderlake: Enable the PCH HDA	V Sowmya
2020-11-30	soc/intel/alderlake: Add initial chipset.cb	Tim Wawrzynczak
2020-11-29	soc/intel: Configure P2SB before other PCH controllers	Furquan Shaikh
2020-11-29	soc/intel/alderlake: Add lp5_ccc_config to the board memory configuration	Sridhar Siricilla
2020-11-23	soc/intel/alderlake: Update UART0 GPIO as per latest schematics	Subrata Banik
2020-11-23	soc/intel/alderlake: Update DCACHE_BSP_STACK_SIZE and DCACHE_RAM_SIZE	Subrata Banik
2020-11-22	soc/intel/alderlake: Fix overlapping memory address used for early GSPI2 and ...	Bora Guvendik
2020-11-20	soc/intel/common/acpi,mb/*: replace the two obsolete LPID with PEPD	Michael Niewöhner
2020-11-12	soc/intel/alderlake: Add PCH ID 0x5181	Subrata Banik
2020-11-07	mb/intel: Enable ALC711 Audio codec over SNDW0 link	Sridhar Siricilla
2020-11-03	soc/intel: Select SOC_INTEL_COMMON_BLOCK_CAR as per alphabetical order	Subrata Banik
2020-11-02	soc/intel: Use of common reset code block	Subrata Banik
2020-10-29	mb/intel/adlrvp: Add dq_pins_interleaved into 'struct mb_cfg'	Subrata Banik
2020-10-28	soc/intel: deduplicate ACPI timer emulation	Michael Niewöhner
2020-10-26	mb/*,soc/intel: drop the obsolete dt option `speed_shift_enable`	Michael Niewöhner
2020-10-26	soc/intel: drop unneeded ISST configuration code	Michael Niewöhner
2020-10-25	soc/intel/alderlake/romstage: Skip GPIO configuration from FSP	Subrata Banik
2020-10-24	{cpu,soc}/intel: deduplicate cpu code	Michael Niewöhner
2020-10-21	soc/intel: convert XTAL frequency constant to Kconfig	Michael Niewöhner
2020-10-21	soc/intel/common: add Kconfig for PM Timer emulation support	Michael Niewöhner
2020-10-19	soc/intel/*: drop useless XTAL shutdown qualification code	Michael Niewöhner
2020-10-17	cpu/intel,soc/intel: drop Kconfig for hyperthreading	Michael Niewöhner
2020-10-14	soc/intel/alderlake: Enable TME for Alder Lake	Subrata Banik
2020-10-08	soc/intel: Make use of common gfx.asl	Subrata Banik
2020-10-06	soc/intel/alderlake/ramstage: Fix compilation issue	Subrata Banik
2020-10-06	soc/intel/alderlake/acpi: Add SoC ACPI directory for ADL	Subrata Banik
2020-10-05	soc/intel: remove duplicate weak versions of mainboard_get_dram_part_num()	Nick Vaccaro
2020-10-05	soc: move mainboard_get_dram_part_num prototype to memory_info.h	Nick Vaccaro
2020-10-05	mb, soc: change mainboard_get_dram_part_num() prototype	Nick Vaccaro
2020-10-03	soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage	Subrata Banik
2020-10-02	drivers/spi: Add BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES config	Shelley Chen
2020-09-27	soc/intel/alderlake: Add GPIOs for Alder Lake SOC	Subrata Banik
2020-09-24	soc/intel/alderlake: Select ACPI_INTEL_HARDWARE_SLEEP_VALUES	Angel Pons
2020-09-24	soc/intel/alderlake/romstage: Fix compilation issue	Subrata Banik
2020-09-22	Revert "soc/intel: Refactor do_global_reset() function"	Furquan Shaikh
2020-09-21	soc/intel: Refactor do_global_reset() function	Subrata Banik
2020-09-19	soc/intel/common/block/cse: Refactor cse_request_global_reset() function	Subrata Banik
2020-09-15	soc/intel/alderlake/romstage: Do initial SoC commit till romstage	Subrata Banik
2020-09-10	soc/intel/alderlake: Rename pch_init() code	Subrata Banik
2020-09-09	vendorcode/intel/fsp/fsp2_0/adl: Add FSP header file version 1332	Subrata Banik
2020-09-05	soc/intel/alderlake/bootblock: Do initial SoC commit till bootblock	Subrata Banik