| Age | Commit message (Expand) | Author |
|---|---|---|
| 2022-02-02 | soc/intel/alderlake: Use PMC IPC to disable HECI1 | Subrata Banik |
| 2022-02-02 | soc/intel/common/cse: Rework heci_disable function | Subrata Banik |
| 2022-01-25 | soc/intel/adl: Replace dt `HeciEnabled` by `HECI1 disable` config | Subrata Banik |
| 2021-05-07 | soc/intel/{adl,tgl,jsl}: Add smihandler_soc_disable_busmaster | Kane Chen |
| 2020-10-03 | soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage | Subrata Banik |
 |
index : coreboot.git | |
| my copy of coreboot | gitea |
| aboutsummaryrefslogtreecommitdiff |