Age | Commit message (Expand) | Author |
2023-08-03 | soc/intel/alderlake/meminit.c: Guard CsPiStartHighinEct properly | Michał Żygowski |
2023-07-31 | soc/intel/alderlake: Allow channel 0 for DDR5 memory-down | Jeremy Soller |
2023-07-18 | soc/intel/alderlake: Hook up CsPiStartHighinEct UPD | Kane Chen |
2023-03-04 | soc/intel/alderlake: Allow channel 0 for memory-down | Tim Crawford |
2022-08-12 | soc/intel/alderlake: Fix DDR5 channel mapping | Angel Pons |
2022-08-02 | soc/intel/alderlake: Configure DDR5 Physical channel width to 64 | Meera Ravindranath |
2022-03-15 | {mb, soc}: Move mrc_cache invalidating logic into `memory` common code | Subrata Banik |
2022-03-15 | soc/intel/common: Pass `FSPM_UPD *` argument for spd functions | Subrata Banik |
2022-03-15 | {mb, soc}: Change `memcfg_init()` and `variant_memory_init()` prototype | Subrata Banik |
2022-03-02 | mb, soc: Add the SPD_CACHE_ENABLE | Zhuohao Lee |
2022-02-21 | soc/intel/alderlake: Make clang static assert happy | Arthur Heymans |
2022-01-13 | vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2511_04 | Nick Vaccaro |
2021-07-13 | soc/intel/alderlake: Implement WA for DDR5 DIMM modules | Meera Ravindranath |
2021-05-16 | soc/intel/alderlake: Update meminit code due to upd changes FSP 2147 onwards | Bora Guvendik |
2021-05-16 | vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2162_00 | Ronak Kanabar |
2021-05-10 | soc/intel/adl: Allow mainboard to fill CmdMirror and DqDqsRetraining | Maulik V Vaghela |
2021-03-26 | soc/intel/alderlake: Add provision to override Rcomp settings | Subrata Banik |
2021-03-26 | soc/intel/alderlake: Align RcompResistor definition as per MRC | Subrata Banik |
2021-01-25 | soc/intel/adl and mb/intel/adlrvp: Use the newly added meminit block driver | Furquan Shaikh |
2020-11-29 | soc/intel/alderlake: Add lp5_ccc_config to the board memory configuration | Sridhar Siricilla |
2020-10-29 | mb/intel/adlrvp: Add dq_pins_interleaved into 'struct mb_cfg' | Subrata Banik |
2020-09-15 | soc/intel/alderlake/romstage: Do initial SoC commit till romstage | Subrata Banik |