index
:
coreboot.git
macbookair5_2
macbookpro10_1
main
master
mbp101_medisable
mbp101_medisable_1
mbp82
x230
my copy of coreboot
User &
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
src
/
soc
/
intel
/
alderlake
/
meminit.c
Age
Commit message (
Expand
)
Author
2022-02-21
soc/intel/alderlake: Make clang static assert happy
Arthur Heymans
2022-01-13
vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2511_04
Nick Vaccaro
2021-07-13
soc/intel/alderlake: Implement WA for DDR5 DIMM modules
Meera Ravindranath
2021-05-16
soc/intel/alderlake: Update meminit code due to upd changes FSP 2147 onwards
Bora Guvendik
2021-05-16
vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2162_00
Ronak Kanabar
2021-05-10
soc/intel/adl: Allow mainboard to fill CmdMirror and DqDqsRetraining
Maulik V Vaghela
2021-03-26
soc/intel/alderlake: Add provision to override Rcomp settings
Subrata Banik
2021-03-26
soc/intel/alderlake: Align RcompResistor definition as per MRC
Subrata Banik
2021-01-25
soc/intel/adl and mb/intel/adlrvp: Use the newly added meminit block driver
Furquan Shaikh
2020-11-29
soc/intel/alderlake: Add lp5_ccc_config to the board memory configuration
Sridhar Siricilla
2020-10-29
mb/intel/adlrvp: Add dq_pins_interleaved into 'struct mb_cfg'
Subrata Banik
2020-09-15
soc/intel/alderlake/romstage: Do initial SoC commit till romstage
Subrata Banik