| Age | Commit message (Expand) | Author |
|---|---|---|
| 2022-03-30 | soc/intel/alderlake: Log CSE RO write protection info for ADL | Sridhar Siricilla |
| 2022-01-02 | soc/intel/{adl,ehl,tgl}: Rename spi_protection_mode to mfg_mode | Subrata Banik |
| 2020-10-03 | soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage | Subrata Banik |
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index : coreboot.git | |
| my copy of coreboot | User & |
| summaryrefslogtreecommitdiff |