summaryrefslogtreecommitdiff
path: root/src/soc/intel/alderlake/include
AgeCommit message (Expand)Author
2020-12-23soc/intel/alderlake: Add SPI DMI Destination IDSubrata Banik
2020-11-29soc/intel/alderlake: Add lp5_ccc_config to the board memory configurationSridhar Siricilla
2020-10-29mb/intel/adlrvp: Add dq_pins_interleaved into 'struct mb_cfg'Subrata Banik
2020-10-24{cpu,soc}/intel: deduplicate cpu codeMichael Niewöhner
2020-10-21soc/intel: convert XTAL frequency constant to KconfigMichael Niewöhner
2020-10-06soc/intel/alderlake/ramstage: Fix compilation issueSubrata Banik
2020-10-05soc: move mainboard_get_dram_part_num prototype to memory_info.hNick Vaccaro
2020-10-05mb, soc: change mainboard_get_dram_part_num() prototypeNick Vaccaro
2020-10-03soc/intel/alderlake/ramstage: Do initial SoC commit till ramstageSubrata Banik
2020-09-27soc/intel/alderlake: Add GPIOs for Alder Lake SOCSubrata Banik
2020-09-15soc/intel/alderlake/romstage: Do initial SoC commit till romstageSubrata Banik
2020-09-10soc/intel/alderlake: Rename pch_init() codeSubrata Banik
2020-09-05soc/intel/alderlake/bootblock: Do initial SoC commit till bootblockSubrata Banik