coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2021-06-25	soc/intel/alderlake: Fix the typo for FSP_S_CONFIG param	V Sowmya
2021-06-24	soc/intel/alderlake: Refactor soc_silicon_init_params function	Subrata Banik
2021-06-24	soc/intel/alderlake: Rename FSP_S_CONFIG variable from params to s_cfg	Subrata Banik
2021-06-24	soc/intel/alderlake: Refactor platform_fsp_silicon_init_params_cb function	Subrata Banik
2021-06-23	soc/intel/alderlake: Use devfn_disable() function for XDCI	Subrata Banik
2021-06-18	soc/intel/alderlake: Add TBT PCIe root ports enablement	Bernardo Perez Priego
2021-06-16	soc/intel/alderlake: Make use of is_devfn_enabled() function	Subrata Banik
2021-06-07	soc/intel: Drop unused lpss functions	Furquan Shaikh
2021-05-18	soc/intel/alderlake: mb/intel/sm: Add tcss code	Deepti Deshatty
2021-04-16	soc/intel/alderlake: Allow devicetree to fill UPD related to TCSS OC	Maulik V Vaghela
2021-03-15	soc/intel/alderlake: Add CNVi Bluetooth flag at devicetree entry	Cliff Huang
2021-03-08	soc/intel/alderlake: Set LidStatus UPD if RUN_FSP_GOP selected	Ronak Kanabar
2021-02-05	soc/intel/alderlake: Refactor PCIE port config	Eric Lai
2021-01-10	soc/intel/alderlake: Refactor SoC code to maintain CPU and PCH PCIE RPs	Subrata Banik
2021-01-06	soc/intel/alderlake: Update CPU microcode patch base address/size	Subrata Banik
2020-10-03	soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage	Subrata Banik