| Age | Commit message (Expand) | Author |
|---|---|---|
| 2021-05-18 | soc/intel/alderlake: mb/intel/sm: Add tcss code | Deepti Deshatty |
| 2021-04-16 | soc/intel/alderlake: Allow devicetree to fill UPD related to TCSS OC | Maulik V Vaghela |
| 2021-03-15 | soc/intel/alderlake: Add CNVi Bluetooth flag at devicetree entry | Cliff Huang |
| 2021-03-08 | soc/intel/alderlake: Set LidStatus UPD if RUN_FSP_GOP selected | Ronak Kanabar |
| 2021-02-05 | soc/intel/alderlake: Refactor PCIE port config | Eric Lai |
| 2021-01-10 | soc/intel/alderlake: Refactor SoC code to maintain CPU and PCH PCIE RPs | Subrata Banik |
| 2021-01-06 | soc/intel/alderlake: Update CPU microcode patch base address/size | Subrata Banik |
| 2020-10-03 | soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage | Subrata Banik |
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index : coreboot.git | |
| my copy of coreboot | User & |
| summaryrefslogtreecommitdiff |