| Age | Commit message (Expand) | Author |
|---|---|---|
| 2021-02-05 | soc/intel/alderlake: Refactor PCIE port config | Eric Lai |
| 2021-01-10 | soc/intel/alderlake: Refactor SoC code to maintain CPU and PCH PCIE RPs | Subrata Banik |
| 2021-01-06 | soc/intel/alderlake: Update CPU microcode patch base address/size | Subrata Banik |
| 2020-10-03 | soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage | Subrata Banik |
 |
index : coreboot.git | |
| my copy of coreboot | gitea |
| aboutsummaryrefslogtreecommitdiff |