index
:
coreboot.git
macbookair5_2
macbookpro10_1
main
master
mbp101_medisable
mbp101_medisable_1
mbp82
x230
my copy of coreboot
User &
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
src
/
soc
/
intel
/
alderlake
/
finalize.c
Age
Commit message (
Expand
)
Author
2024-10-07
soc/intel/adl to jsl: Explicitly include static.h for config_of_soc
Nicholas Chin
2023-06-23
commonlib/console/post_code.h: Change post code prefix to POSTCODE
lilacious
2022-12-15
treewide: Remove unused 'include <arch/io.h>'
Elyes Haouas
2022-04-27
soc/intel/cmn/lockdown: Perform SA lockdown configuration
Subrata Banik
2022-02-18
soc/intel/alderlake: Skip FSP Notify APIs
Subrata Banik
2022-02-04
soc/intel/{adl, common}: Add routines into CSE IA-common code
Subrata Banik
2022-02-02
soc/intel/alderlake: Use PMC IPC to disable HECI1
Subrata Banik
2021-11-22
soc/intel/{adl,ehl,jsl,tgl}: Remove unused header `thermal.h`
Subrata Banik
2021-10-17
soc/intel: move disabling of PM Timer to SoC PMC code
Michael Niewöhner
2021-10-12
soc/intel: replace dt option PmTimerDisabled by Kconfig
Michael Niewöhner
2021-10-06
soc/intel/alderlake: Perform `heci_finalize` prior to booting to OS
Subrata Banik
2021-09-30
soc/intel/alderlake: Perform `soc_finalize` at entry of BS_PAYLOAD_BOOT
Subrata Banik
2021-08-26
soc/intel/alderlake: Lock PAM registers in finalize
Tim Wawrzynczak
2021-08-04
Move post_codes.h to commonlib/console/
Ricardo Quesada
2020-10-19
soc/intel/*: drop useless XTAL shutdown qualification code
Michael Niewöhner
2020-10-03
soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage
Subrata Banik