| Age | Commit message (Expand) | Author |
|---|---|---|
| 2021-04-21 | soc/intel: Replace open-coded buffer length calculation | Angel Pons |
| 2021-03-27 | soc/intel: Rename and move MISCCFG_GPIO_PM_CONFIG_BITS definition to soc/gpio.h | Subrata Banik |
| 2021-02-24 | soc/intel/{adl,jsl,ehl,tgl}: Remove ITSS polarity restore | Aamir Bohra |
| 2021-02-09 | soc/amd,intel: Drop s3_resume parameter on FSP-S functions | Kyösti Mälkki |
| 2021-01-18 | soc/intel/alderlake: Update PCH and CPU PCIe RP table | Eric Lai |
| 2020-12-30 | soc/intel: hook up new gpio device in the soc chips | Michael Niewöhner |
| 2020-10-03 | soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage | Subrata Banik |
 |
index : coreboot.git | |
| my copy of coreboot | User & |
| summaryrefslogtreecommitdiff |