coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2021-11-15	soc/intel/alderlake: Fix build failure with enabled CSE stitching	Bernardo Perez Priego
2021-11-15	Reland "vboot_logic: Set VB2_CONTEXT_EC_TRUSTED in verstage_main"	Hsuan-ting Chen
2021-10-26	cpu/x86: Introduce and use `CPU_X86_LAPIC`	Felix Held
2021-10-25	cpu,soc/x86: always include cpu/x86/mtrr on x86 CPUs/SoCs	Felix Held
2021-10-19	soc/intel/alderlake: Enable support for CSE stitching	Furquan Shaikh
2021-10-15	Revert "vboot_logic: Set VB2_CONTEXT_EC_TRUSTED in verstage_main"	Hsuan-ting Chen
2021-09-16	vboot_logic: Set VB2_CONTEXT_EC_TRUSTED in verstage_main	Hsuan Ting Chen
2021-09-08	cpu/x86/tsc: Deduplicate Makefile logic	Angel Pons
2021-08-12	soc/intel/alderlake: Configure the SKU specific parameters for VR domains	V Sowmya
2021-05-18	cpu/x86: Only include smm code if CONFIG_HAVE_SMI_HANDLER=y	Arthur Heymans
2021-05-06	soc/intel/alderlake: Add CrashLog implementation for Intel ADL	Francois Toguo
2021-04-23	soc/intel/alderlake: Add DPTF HIDs for Alder Lake SoC	Sumeet R Pawnikar
2021-03-30	soc/intel/alderlake: Enable logging of wake sources for S0ix	Sugnan Prabhu S
2021-03-03	soc/intel: Factor out common smmrelocate.c	Angel Pons
2021-03-01	soc/intel: Drop `bootblock_cpu_init()` function	Angel Pons
2021-02-24	soc/intel/alderlake: Add soc_get_xhci_usb_info() for elog support	Tim Wawrzynczak
2021-01-18	soc/intel/alderlake: Update PCH and CPU PCIe RP table	Eric Lai
2020-10-03	soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage	Subrata Banik
2020-09-27	soc/intel/alderlake: Add GPIOs for Alder Lake SOC	Subrata Banik
2020-09-15	soc/intel/alderlake/romstage: Do initial SoC commit till romstage	Subrata Banik
2020-09-05	soc/intel/alderlake/bootblock: Do initial SoC commit till bootblock	Subrata Banik