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2023-02-04soc/amd: Use common reset code for PHX & Glinda SoCsMartin Roth
This switches the Phoenix & Glinda SoCs to use the common reset code. Cezanne and newer do not support warm reset, so use cold resets in all cases (including the OS). Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I4593fa9766ac9e988722a02e355c971e147b8fae Reviewed-on: https://review.coreboot.org/c/coreboot/+/72754 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-04soc/amd: Use common reset code for CZN & MDN SoCsMartin Roth
This switches the Cezanne & Mendocino SoCs to use the common reset code. This patch does not change any behavior on those chips. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ie05c790573e4e68f3ec91bacffcc7d7efb986d79 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72659 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-04soc/amd: Create AMD common reset codeMartin Roth
This allows us to use the same file for PCO, CZN, MDN, PHX, & Glinda. PCO supports the warm reset, and future chips can support it by setting the SOC_AMD_SUPPORTS_WARM_RESET option. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ib6459e7ab82aacbe57b4c2fc5bbb3759dc5266f7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72658 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-01soc/amd/mendocino: Force resets to be coldMartin Roth
Like Cezanne, Mendocino does not support warm resets. Change all resets (including resets in the OS) to cold resets (like Cezanne). BUG=b:248221908 TEST=Run suspend_stress_test, then reboot Change-Id: I1fbb4cc6eb6e6de9616d00d0191ccf3c0ac55278 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72486 Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com>
2023-02-01treewide: Remove duplicated include <device/pci.h>Elyes Haouas
<device/pci.h> chain-includes <device/pci_def.h> & <device/pci_type.h>. Change-Id: I4e5999443e81ee1c4b1fd69942050b47f21f42f8 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72626 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-31soc/amd/glinda/acpi: use acpigen_write_processor_deviceFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iec9cf7c195fa5cb5c8d992aeab400d05cbe801c2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72494 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-01-31soc/amd/phoenix/acpi: use acpigen_write_processor_deviceFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I103cdce8c23ff4adbf1057fa26bd67275f2ab0e5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72493 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-01-31soc/amd/mendocino/acpi: use acpigen_write_processor_deviceFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I036dcddf89e8d865d0dc3ef0bd9e48842d8bf6c3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72492 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-01-31soc/amd/cezanne/acpi: use acpigen_write_processor_deviceFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I77a91c0a6d937772bf25fa936cec8a710b9acf72 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72491 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-01-31soc/amd/picasso/acpi: use acpigen_write_processor_deviceFelix Held
In CB:71614 Kyösti pointed out that ACPI_GPE0_BLK is the wrong address to assign to proc_blk_addr; the correct one would be ACPI_CPU_CONTROL. When looking a bit closer into this, it turned out that acpigen_write_processor is generating deprecated AML opcodes, so replace the acpigen_write_processor call with a call to the newly added acpigen_write_processor_device function that also doesn't have the proc_blk_addr and proc_blk_len parameters. The information about the IO port for entering C-states is already written into an SSDT by acpigen_write_CST_package which is likely also the reason why the wrong proc_blk_addr value wasn't noticed for a very long time. TEST=Mandolin still boots Ubuntu 22.04 LTS and Windows 10 and no possibly related errors show up. Linux gets the expected C-state information from the _CST package inside the processor device scope. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie67416e19e431029dd12da66ad44ddfa8586df03 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72490 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-01-31soc/amd/common/block/include/acpi: drop MMIO_ACPI_CPU_CONTROL defineFelix Held
This register isn't used in coreboot and isn't defined in the Picasso PPR #55570 Rev 3.18. To enter a lower C-state, a read request to a special IO port is done. The base address of this group of IO ports is configured in set_cstate_io_addr via the MSR_CSTATE_ADDRESS and that read won't leave the CPU. IIRC trying to put the MMIO mapping for entering the lower C-states into the _CST package didn't work as expected when it was tried on I think Cezanne. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib189993879feaa0a22f6810c4bd5c1a0bc8c5a27 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72497 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-01-23soc/amd/mendocino/acpi: remove RTC wake workaroundFelix Held
Commit 78ee4889dc32 ("soc/amd/cezanne/acpi: Add support for RTC workaround") added a workaround for the Cezanne silicon. This was copied to the Mendocino code, but from both the discussion in b:209705576 and the referenced amd_pmc_verify_czn_rtc function in drivers/platform/x86/ amd/pmc.c that is only called if pdev->cpu_id == AMD_CPU_ID_CZN is true Mendocino doesn't need that workaround, so remove it. TEST=Running suspend_stress_test -c 5 on Chausie shows no errors Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I7d0b35ef8cf88ff0b9bed8820b8da32c2058cc1b Reviewed-on: https://review.coreboot.org/c/coreboot/+/72091 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-22soc/amd/*: Enable override of MAINBOARD_BLOBS_DIRFred Reitberger
MAINBOARD_BLOBS_DIR is defined the same way by picasso/cezanne/mendocino/phoenix/glinda and unused by stoneyridge, so move it to a common area. This makefile variable is currently only used to locate APCB blobs for the different mainboards. Add a Kconfig option to point to the APCB blobs directory. This allows simple overriding to locations such as site-local. TEST=Timeless builds Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I0702fdb97fbc2c73d97994ab4d5161ff0f467518 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69410 Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-22soc/amd/stoneyridge,sb/amd/pi/hudson: Remove unused AHCI_ROM_IDElyes Haouas
Change-Id: I0a3a3d8b3f898dc147eff54fe4ae2611139951ac Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72143 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-22soc/amd/stoneyridge: clean up global NVSFelix Held
Remove the unused fields that were previously used for PCNT and PWRS. The LIDS field is only used in the ACPI code, but keep if for now, since it would require a bigger rework to remove it from the global NVS. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6b172214998818f841f5694f47815eddfaf9deaa Reviewed-on: https://review.coreboot.org/c/coreboot/+/72139 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-22soc/amd/picasso: clean up global NVSFelix Held
Remove the unused fields that were previously used for PCNT and PWRS. The LIDS field is only used in the ACPI code, but keep if for now, since it would require a bigger rework to remove it from the global NVS. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I79509146431e4584e50af4477f3f50dc3cf01bcf Reviewed-on: https://review.coreboot.org/c/coreboot/+/72138 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-20soc/amd/glinda,mendocino,phoenix/espi_util: add comment about registerFelix Held
Even though the register name begins with ESPI, it resides in the SPI registers and not in the eSPI registers, so add a comment to point this out to hopefully avoid some confusion. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I9f8d15ceb98f51aad0816021f98ec5c78953e7f3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72122 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-01-20soc/amd/glinda/espi_util: update file to match documentationFelix Held
Checked against document #57396 revision 1.52 and removed the DIS_ESPI_MASCTL_REG_WR define, since that bit is marked as reserved. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3e8b1c65118b4e85e7934e822a7a7e329746a88d Reviewed-on: https://review.coreboot.org/c/coreboot/+/72121 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-01-20soc/amd/phoenix/espi_util: remove TODO after checkingFelix Held
Checked against both documents #57019 revision 1.59 and #57396 revision 1.50 that the definitions and the code still apply to Phoenix. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id65301ec730793f41044696f2e99356f2e899137 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72120 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-01-20soc/amd/glinda: clean up global NVSFelix Held
From Cezanne on, the TMPS, TCRT and TPSV fields are unused in both the C and ACPI code, so they can be removed. Also remove the unused fields that were previously used for PCNT and PWRS. The LIDS field is only used in the ACPI code, but keep if for now, since it would require a bigger rework to remove it from the global NVS. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie1c3c25591deadb27b7bf38a81dcd6fe746de55b Reviewed-on: https://review.coreboot.org/c/coreboot/+/72096 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-20soc/amd/phoenix: clean up global NVSFelix Held
From Cezanne on, the TMPS, TCRT and TPSV fields are unused in both the C and ACPI code, so they can be removed. Also remove the unused fields that were previously used for PCNT and PWRS. The LIDS field is only used in the ACPI code, but keep if for now, since it would require a bigger rework to remove it from the global NVS. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5a9b0a24f57a81b98c7553517fe5f25ff63c5316 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72095 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-20soc/amd/mendocino: clean up global NVSFelix Held
From Cezanne on, the TMPS, TCRT and TPSV fields are unused in both the C and ACPI code, so they can be removed. Also remove the unused fields that were previously used for PCNT and PWRS. The LIDS field is only used in the ACPI code, but keep if for now, since it would require a bigger rework to remove it from the global NVS. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I884d6a7dedb73028f8942fdda86b0c9910fa996a Reviewed-on: https://review.coreboot.org/c/coreboot/+/72094 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-20soc/amd/cezanne: clean up global NVSFelix Held
From Cezanne on, the TMPS, TCRT and TPSV fields are unused in both the C and ACPI code, so they can be removed. Also remove the unused fields that were previously used for PCNT and PWRS. The LIDS field is only used in the ACPI code, but keep if for now, since it would require a bigger rework to remove it from the global NVS. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib4034e959d167fb1e08ee5b15e21fb93bc89db8a Reviewed-on: https://review.coreboot.org/c/coreboot/+/72093 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-20soc/amd/mendocino/acpi/pci_int_defs: remove TODO after checkingFelix Held
All field definitions in the IndexField object match both the info in the PPR #57243 revision 3.02 and also match the defines in soc/amd/ mendocino/include/soc/amd_pci_int_defs.h. The IndexFieldvonly defines the subset of the IRQ mapping registers that are used or likely needed in the future. This is handled in the same way for the other AMD SoCs. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6b0adfecc99945de69b4853f4423b4c10951d3e5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72092 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-20soc/amd/mendocino: Remove TODO after reviewFred Reitberger
Remove TODO comment after reviewing against mendocino ppr #57243, rev 3.00 BUG=b:263563246 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I9a89751df71eb32b2c8d99c568341dd669b5f065 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72073 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-19soc/amd/stoneyridge/northbridge: use acpi_align_currentFelix Held
Use acpi_align_current to align the ACPI tables on a 16 byte boundary. This changes the alignment of the HEST, IVRS, SRAT and SLIT tables from 8 bytes to 16 bytes. The alignment of the ALIB and PSTATE SSDT tables was already 16 bytes before, so the alignment of those isn't changed. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8933e3731b67012bcae0773db2f7f8de7cd31b56 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72055 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-18soc/amd/common/block/acpi/cppc: drop outdated commentFelix Held
Since commit d5ab24cd4800 ("soc/amd/common/acpi/cppc: add nominal and minimum frequencies") the fields that got added in CPPC version 3 get populated, so remove the now outdated comment about the fields added in version 3 always being set to CPPC_UNSUPPORTED. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4c975b42fc4f67329170801b871d6bbdf9637d04 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72046 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-01-18soc/amd/*/agesa_acpi: add TODO for adding CRAT tableFelix Held
The Picasso SoC code generates a CRAT ACPI table which is not done for Cezanne and newer. A significant part of the Picasso CRAT generation code can likely be moved to the common AMD SoC code and then used in all SoCs, but this still needs to be checked. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8f1ebe74f0376c60396dbd80e64676d1374ed811 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72027 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-18soc/amd/glinda/agesa_acpi: use acpi_align_current to align IVRS & ALIBFelix Held
This changes the alignment of the IVRS table from 8 bytes to 16 bytes and aligns the ALIB table to a 16 byte boundary. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I965791fbbe499702e191dcbf1f5fbfcb5e1bab6b Reviewed-on: https://review.coreboot.org/c/coreboot/+/72026 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-01-18soc/amd/phoenix/agesa_acpi: use acpi_align_current to align IVRS & ALIBFelix Held
This changes the alignment of the IVRS table from 8 bytes to 16 bytes and aligns the ALIB table to a 16 byte boundary. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I766260aefcac6876609d6b45202b41a3e9e44385 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72025 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-01-18soc/amd/mendocino/agesa_acpi: use acpi_align_current to align IVRS&ALIBFelix Held
This changes the alignment of the IVRS table from 8 bytes to 16 bytes and aligns the ALIB table to a 16 byte boundary. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I2b48a7cbed84551e7651992589c38eac54f27d1f Reviewed-on: https://review.coreboot.org/c/coreboot/+/72024 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-01-18soc/amd/cezanne/agesa_acpi: use acpi_align_current to align IVRS & ALIBFelix Held
This changes the alignment of the IVRS table from 8 bytes to 16 bytes and aligns the ALIB table to a 16 byte boundary. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4de66ab11508814da5d7fb440a1083a52551bcf5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72023 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-01-18soc/amd/picasso/agesa_acpi: align ALIB with acpi_align_currentFelix Held
This makes sure that the ALIB table is aligned on a 16 byte boundary. TEST=Mandolin still boots Linux and the position and size of the ACPI tables in memory shown by dmesg hasn't changed. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I90781ef98b729c0a8d1f5dde46fc9ca5d08618b3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72022 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-01-18soc/amd/picasso/agesa_acpi: use acpi_align_current to align CRAT & IVRSFelix Held
This changes the alignment of the CRAT and IVRS tables from 8 bytes to 16 bytes. TEST=Mandolin still boots Linux and the position and size of the ACPI tables in memory shown by dmesg hasn't changed. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I88df331c8410d8dca41a414543f051f5e4656ff1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72021 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-01-18soc/amd: Include <gpio.h> instead of <soc/gpio.h>Elyes Haouas
<gpio.h> chain-include <soc/gpio.h>. Change-Id: I112e41ad4c7ee638954dfe3f1ddfeb10c138459a Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71807 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-01-17soc/amd: introduce and use common amd_cpu_bus_ops structFelix Held
The device operations for the CPU bus are identical for all AMD SoCs, so introduce a common device operations struct for this and use it in all AMD SoC's chipset devicetrees as ops for the CPU cluster. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id32f89b8a33db8dbb747b917eeac3009fbae6631 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71998 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-01-17soc/amd: Use fixed EFS location for Phoenix & GlindaMartin Roth
The AMD SoCs no longer have a variable position for EFS - it's now fixed at 0xff020000 - 128KiB into the 16MiB ROM decode region. It's a little more complex than that because the chip can be larger than 16MiB, and the entire ROM can be decoded if mapped above the 4GiB boundary, but we don't currently support doing that in coreboot, so this is enough for now. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I343a875ba9aa8294a090f2eff7b5dfb5e86334f8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71769 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-01-17treewide: Fix old-style declarationsElyes Haouas
Replace old style declaration "const static" with "static const". This to enable "Wold-style-declaration" command option. Change-Id: I757632befed1854f422daaf4dfea58281b16e2f5 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71841 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-16soc/amd/picasso/include/acpi: introduce and use ACPI_SCI_IRQ definitionFelix Held
The newer AMD SoCs define ACPI_SCI_IRQ in the SoC's acpi.h header file and use this definition in the mainboard code, so port this back to Picasso. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib569747aa388d7953e79de747905fb52c2a05e74 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71912 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-01-15soc/amd/mendocino: PSP_INCLUDES_HSPKarthikeyan Ramasubramanian
Select HSP config to indicate that the SoC includes Hardware Security Processor. This will allow PSP verstage to get and report the HSP state. BUG=None TEST=Build Skyrim BIOS image and boot to ChromeOS on Skyrim. Verify that HSP is reported during the boot sequence. Change-Id: I22446c2bd6202529367da040c09449e6b26f9d7a Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71209 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-01-15soc/amd/common/psp_verstage: Report HSP Secure StateKarthikeyan Ramasubramanian
Get Hardware Security Processor(HSP) state in PSP Verstage through the SVC call and report it in cbmem logs. BUG=b:198711349 TEST=Build Skyrim BIOS image and boot to OS in Skyrim. Change-Id: Ic4875d1732f22783a90434329188192b106168f4 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71208 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-01-15vc/amd/*,soc/amd/*: Add SVC call to get HSP Secure StateKarthikeyan Ramasubramanian
Add an SVC call to get the state of Hardware Security Processor (HSP) in AMD SoCs. This SVC call will be used from PSP verstage to get and report HSP state. BUG=b:198711349 TEST=Build Skyrim BIOS image and boot to OS. Ensure that the HSP state is read and reported in the firmware logs. Change-Id: I7fe3363d308a80cc09e6bdadd8d0bb1d67f7d2bf Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71207 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-15soc/amd/mendocino/include/acpi,lpc: remove TODO after reviewFelix Held
Remove TODO comment after checking against Mendocino PPR #57243, rev 3.02. BUG=b:263563246 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie0e35f4c68ec09304eb892888759c7e5ef3dd0ca Reviewed-on: https://review.coreboot.org/c/coreboot/+/71911 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-13soc/amd/phoenix: update mmconf base address and sizeRitul Guru
0xF8000000 was taken from old platform during phoenix porting, updating it to 0xE0000000 to make room for 256 pci busses which is required for usb4 and hotplug support. mmconf size gets set to 0x10000000 when 256 busses are used. Change-Id: Ic143171f5650aff5db48c8f477d7aca3e7f5c1e7 Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71870 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-13soc/amd/glinda: use common SMU S3/4/5 entry message codeFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I62b15d59cc4a5f214e45c3995f651228b1ae6ea7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71900 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-01-13soc/amd/phoenix: use common SMU S3/4/5 entry message codeFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie7ded68f4732ec12a1c7e59445d572763a03c3b9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71879 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-01-13soc/amd/mendocino: use common SMU S3/4/5 entry message codeFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ief1e9c6d6fa0889b947863837bedb2fbdf3120c3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71878 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-01-13soc/amd/cezanne: use common SMU S3/4/5 entry message codeFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4b9f1b71a5f8b2776c8b338351b2cca723d00598 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71877 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-01-13soc/amd/picasso: use common SMU S3/4/5 entry message codeFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iedd99cfb64809c4e111e0931c2260981f465035b Reviewed-on: https://review.coreboot.org/c/coreboot/+/71876 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-01-13soc/amd: introduce common SMU S3/4/5 entry message codeFelix Held
The smu_sx_entry function is identical for all AMD SoCs, so introduce it as common code that can be selected to be included in the build via the SOC_AMD_COMMON_BLOCK_SMU_SX_ENTRY Kconfig option. The only SoC-specific difference in this function is the ID of the SMC_MSG_S3ENTRY message which is defined in each SoC's soc/smu.h include file. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I49758e9333a351d8e50e8f1b53a7f00fbe89866c Reviewed-on: https://review.coreboot.org/c/coreboot/+/71875 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-01-13soc/amd/glinda: Use common fsp-s preloaderFred Reitberger
Use the common preloader for fsp-s Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I32f8ca02c4de9e882f207c2dd2378b6b44dc61ff Reviewed-on: https://review.coreboot.org/c/coreboot/+/71848 Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-13soc/amd/phoenix: Use common fsp-s preloaderFred Reitberger
Use the common preloader for fsp-s Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Iea7011d37667f3f04ce842038346741fba66b1dc Reviewed-on: https://review.coreboot.org/c/coreboot/+/71847 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-12soc/amd/mendocino: Use common fsp-s preloaderFred Reitberger
Use the common preloader for fsp-s Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I74ef10347c37c8371156f89da9f234d170ab1aa6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71846 Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-01-12soc/amd/cezanne: Use common fsp-s preloaderFred Reitberger
Use the common preloader for fsp-s Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Ibbed17445c3cd8fa4da671f2a90532d3c39ad08b Reviewed-on: https://review.coreboot.org/c/coreboot/+/71845 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-01-12soc/amd/common/fsp: Introduce SOC_AMD_COMMON_FSP_PRELOAD_FSPSFred Reitberger
The function to start preloading the fsp-s is identical in cezanne and newer socs, so move it to common with a new Kconfig option to enable it. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Ia572c99928f4a60896b7a861ab6fb3f1257ac1cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/71844 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-01-12soc/amd/mendocino/include/soc/southbridge.h: Use BIT macro for consistencyFred Reitberger
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I2dd17774b79c5adb64c2575ac55dec476c434842 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71843 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-01-12soc/amd/mendocino: Remove TODO after reviewFred Reitberger
Remove TODO comment after reviewing against mendocino ppr #57243, rev 3.00 BUG=b:263563246 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Id517ce6e5f5bee5deffe509d748b16be0eefca96 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71842 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2023-01-12soc/amd/mendocino/include/platform_descriptors: remove TODO after reviewFelix Held
This header file is correct for Mendocino, so remove the TODO. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I85b47491863bff731b86cf0523253cb547dbb76a Reviewed-on: https://review.coreboot.org/c/coreboot/+/71794 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-12treewide: Remove unused <cpu/amd/mtrr.h>Elyes Haouas
Change-Id: Ibff33c08a1d583b19b205a66d5a4267df65ced75 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64940 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-123rdparty/amd_blobs:Advance submodule pointerJason Glenesk
This picks up the following changes: acf73954 phoenix: rename morgana to phoenix a2c15297 mendocino: Upgrade SMU to 90.35.166 28983855 Update Picasso FSP binaries This also updates the phoenix fw.cfg file that points to the submodule. Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I1d04d6232307dc913645a3d60ac3711018e2bdfb Reviewed-on: https://review.coreboot.org/c/coreboot/+/71803 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-12soc/amd: Change Morgana codename to PhoenixMartin Roth
Now that the next generation of APUs is officially announced, we can unmask morgana. The chip formerly known as Morgana is actually Phoenix. Surprise! This patch just changes the name across the entire codebase. Note that the fw.cfg file will stay pointing to the 3rdparty/amd_blobs/morgana/psp directory until the amd_blobs_repo is updated. Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Change-Id: Ie9492a30ae9ff9cd7e15e0f2d239c32190ad4956 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71731 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-10soc/amd/common/fsp/Makefile: Fix an error messageAkihiko Odaki
It used to say "FSP-M binary larger than FSP_M_FILE", but FSP_M_FILE is the binary itself. The binary file size is actually compared with FSP_M_SIZE. Signed-off-by: Akihiko Odaki <akihiko.odaki@gmail.com> Change-Id: If58069944aea8e68117f2ee1d320726d8c6fdfc8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65440 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-01-09treewide: Remove unused <cpu/amd/msr.h>Elyes Haouas
Change-Id: Id24a7c7db24f49672df9d5ceefec5b7596f23e09 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64939 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-01-09soc/amd: Remove dummy SOC_SPECIFIC_OPTIONSElyes Haouas
Change-Id: I080b7b579338c3cf342beabda54f43f525d8b65c Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71679 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-01-09soc/amd/morgana: Double max number of cpus for morganaRitul Guru
Change-Id: I5169a900345e2aabefcf1e2c249ee4bce6dc8fc5 Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71688 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-01-09soc/amd/morgana: update morgana cpuidRitul Guru
Change-Id: Ieaad72a6b964f4b2ab572733694def88e30888a3 Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71689 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-01-09soc/amd/mendocino/Kconfig: Remove TODO after reviewFred Reitberger
Remove TODO comments after reviewing against mendocino ppr #57243, rev 3.00 BUG=263563246 TEST=build skyrim Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Ie56d481dd8b6b4e0a1e3d50f4ce75f50231fe4dc Reviewed-on: https://review.coreboot.org/c/coreboot/+/71719 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-09soc/amd/common/block/graphics: Fix whitespace consistencyFred Reitberger
Replace spaces with tabs for consistency. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I65b9bec7443094dfd2f6b0d6b11e0100023873b2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71721 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-01-04soc/amd/mendocino: Hook up UPD dxio_tx_vboost_enable for PCIe optimizationChris.Wang
Add the UPD dxio_tx_vboost_enable for PCIe optimization. It will impact the PCIe signal integrity, need to double-confirm the SI result after enabling this setting. BUG=b:259622787 BRANCH=none TEST=confirm the setting has been set correspondingly with checking the FSP log. Signed-off-by: Chris.Wang <chris.wang@amd.corp-partner.google.com> Change-Id: I05ae5b3091219e0cb1fe469c929fad6a725db678 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71562 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-03soc/amd/cezanne/psp_verstage/Makefile.inc: Remove path to non-existent ↵Elyes Haouas
directories Found using 'Wmissing-include-dirs' command option. Fix: cc1: error: ../../src/soc/amd/cezanne/psp_verstage/include: No such file or directory [-Werror=missing-include-dirs] Change-Id: I36022a031cc08d2af8b982522b3d6652e679bf14 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71588 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-01-03soc/amd/picasso/psp_verstage/Makefile.inc: Remove path to non-existent ↵Elyes Haouas
directories Found using 'Wmissing-include-dirs' command option. Fix: cc1: error: ../../src/soc/amd/picasso/psp_verstage/include: No such file or directory [-Werror=missing-include-dirs] Change-Id: I7713eef54686c58a83215c461c3274cec89e32b0 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71587 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-01-03soc/amd/mendocino/psp_verstage/Makefile.inc: Remove path to non-existent ↵Elyes Haouas
directory Found using 'Wmissing-include-dirs' command option. Fix: cc1: error: ../../src/soc/amd/mendocino/psp_verstage/include: No such file or directory [-Werror=missing-include-dirs] Change-Id: I1cc084abc7a9bfed760350f304dd074081a7eebf Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71586 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-12-27tree/acpi: Replace constant "Zero" with actual numberFelix Singer
Change-Id: I5a3e3506415f424bf0fdd48fc449520a76622af5 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71525 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-27{acpi,arch,soc}/acpi: Replace constant "One" with actual numberFelix Singer
Change-Id: I3dfd7dd1de3bd27c35c195bd43c4a5b8c5a2dc53 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71522 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-24soc/amd/mendocino: Split the EFS from the AMDFW bodyKarthikeyan Ramasubramanian
Contents of unsigned AMDFW in RW sections are verified twice in PSP verstage - first time by vboot verifying the firmware body, second time by CBFS verification while the file is loaded to update PSP about the boot region. This redundant verification adds to boot time. Minimize the redundancy by splitting the EFS header from the AMDFW body and keep them as 2 separate CBFS files. This helps to improve the boot time by another 25 ms. BUG=None TEST=Build Skyrim BIOS image and boot to OS. Observe boot time improvement of ~25ms. Before: 6:end of verified boot 363,676 (16) 11:start of bootblock 641,392 (277,716) After: 6:end of verified boot 361,655 (16) 11:start of bootblock 616,967 (255,312) Change-Id: Ib18a4f5c6781e5a7868e9395c0f1212da0823100 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70839 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-21soc/amd/common/psp_verstage: Report previous boot statusKarthikeyan Ramasubramanian
Add support to report previous PSP boot failure to verified boot. This is required specifically on mainboards where the signed AMDFW blobs are excluded from vboot verification. BUG=b:242825052 TEST=Build Skyrim BIOS image and boot to OS in Skyrim. Corrupt either one of SIGNED_AMDFW_A/B sections or both the sections to ensure that the appropriate FW slot is chosen. Cq-Depend: chromium:4064425 Change-Id: Iada0ec7c373db75765ba42cb531b16c2236b6cc3 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70382 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-21vc/amd,soc/amd/mendocino: Add SVC_CMD_GET_PREV_BOOT_STATUSKarthikeyan Ramasubramanian
Add an SVC command to get the previous boot status. If there is any pre-x86 boot failure in the previous boot cycle, PSP stores it in warm reset persistent register and triggers a warm reset. PSP verstage on the subsequent boot gets the previous boot status and reports any failure to the vboot before a FW slot is selected. BUG=b:242825052 TEST=Build Skyrim BIOS image and boot to OS in Skyrim. Trigger a failure scenario by corrupting certain firmware blobs and observe that PSP reports the failure boot status. On a normal boot, observed that PSP reports successful boot. Change-Id: I440deee560b72c80491bfdd7fda38a1c3a4299e5 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70381 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-20soc/amd/mendocino: add dptc tablet mode supportChris.Wang
add dptc support for different power parameter on tablet/clamshell mode. BUG=b:257187831 BRANCH=none TEST=validate the parameter change for each mode by AGT. Signed-off-by: Chris.Wang <chris.wang@amd.corp-partner.google.com> Change-Id: I96e04d113d18b42f3457056a5e4fa311ceccffb3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70670 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
2022-12-20src/soc: Remove unneeded <assert.h>Elyes Haouas
As _Static_assert() is a compiler built-in, <assert.h> is not needed. Change-Id: I578b4bf286538d0606569d19ec760a1846c8145b Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70904 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-16soc/amd/common/block/i2c: don't call die() when MMIO address is NULLFelix Held
There's no need to call die() in the case that the MMIO address of the I2C controller is NULL, so handle this case by returning a failure instead. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I12c143916ad551c56cc4ff75ae23754018817505 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70827 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-14soc/amd/morgana/Kconfig: Remove TODO after reviewFred Reitberger
Remove more TODO comments after reviwing against morgana ppr #57396, rev 1.52 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I7fd9666a69d9a2b0902fa28ab0af0187198297ec Reviewed-on: https://review.coreboot.org/c/coreboot/+/70466 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-14soc/amd/common/block/espi_util: drop unneeded check in espi_get_configFelix Held
Since soc_get_common_config will either return a valid pointer or cause a linking error, this function will also return a valid pointer or cause a linking error, so no need for additional runtime checks. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I99661247b9f8f47a708e3a6ff3f9e5359b505509 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70739 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-12-14soc/amd/*/config: drop invalid commentFelix Held
Since commit 28e61f16341f ("device: Use __pci_0_00_0_config in config_of_soc()") config_of_soc() was changed form being an actual function to a macro for the __pci_0_00_0_config struct pointer generated by util/sconfig. This change didn't only improve linker optimizations, but also turned runtime errors into link-time errors, so it's guaranteed that __pci_0_00_0_config won't be NULL and config_of_soc() won't "return" NULL. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id99ceaa9f7a70788da3f3068fb3da92d34fb6361 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70732 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-12-14soc/amd/common/block/espi_util: make espi_set_initial_config non-fatalFelix Held
Improve the espi_set_initial_config implementation so that a failure in there due to an invalid configuration won't call die() and stop booting at this point, but return an error to the caller so that the rest of the eSPI configuration will be skipped. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I97f730778a190c4485c4ffe93edf19bcbaa45392 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70731 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-12-14soc/amd/common/block/lpc/espi_util: make eSPI pin setup failure nonfatalFelix Held
Improve the eSPI pin configuration setup so that a failure in there won't call die() and stop booting at this point, but return an error to the caller so that the rest of the eSPI configuration will be skipped. This will prevent an early boot failure if the EC is missing or the eSPI interface is in a non-functional state. Also slightly shorten the function names so that the code still fits into 96 chars. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ice2d3a791d6a464eff4fb69d02aeca0bfe580be2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70730 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
2022-12-13soc/amd/morgana: Enable GPP clk req disablingFred Reitberger
Enable GPP clk req disabling on morgana after reviewing against morgana ppr #57396, rev 1.52 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Id2502137486df7a8b0ac6a4b3e061b25b23e2e51 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70465 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-13soc/amd/morgana: Update pci int defsFred Reitberger
Update pci int defs per preview of next ppr after rev 1.52, #57396 Update birman and mayan mainboards to remove deleted PIRQs. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I10e13784761f0b9245f0ca10e3cd07d396ec4224 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70379 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-12vc/amd/fsp/glinda/FspmUpd: don't use pointers for usb_phy configFelix Held
The size of a pointer changes between a 32 and 64 bit coreboot build. In order to be able to use a 32 bit FSP in a 64 bit coreboot build, change the pointer in the UPDs to a uint32_t to always have a 32 bit field in the UPD for this. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5db2587ff74432a0ce1805d8d7ae76d650693eea Reviewed-on: https://review.coreboot.org/c/coreboot/+/70506 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-12-12soc/amd/morgana: Remove emmc selectFred Reitberger
Morgana does not have emmc, so do not select it. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Ib75618c137e825befc7384275f1a4ef9b5137b09 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70477 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-12vc/amd/fsp/morgana/FspmUpd: don't use pointers for usb_phy configFelix Held
The size of a pointer changes between a 32 and 64 bit coreboot build. In order to be able to use a 32 bit FSP in a 64 bit coreboot build, change the pointer in the UPDs to a uint32_t to always have a 32 bit field in the UPD for this. Also make sure that the address of the lcl_usb_phy struct is located below the 4GB boundary, so that the truncation to 32 bits won't result in pointing to a different memory location than intended. In this error case, which I don't expect to happen, print an error and write 0 to mcfg->usb_phy_ptr so that the FSP will use its default values. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1394aa6ef5f401e0c7bdd4861f1e28ae46e56e4f Reviewed-on: https://review.coreboot.org/c/coreboot/+/70505 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-10treewide: Include <device/mmio.h> instead of <arch/mmio.h>Elyes Haouas
<device/mmio.h>` chain-include `<arch/mmio.h>: https://doc.coreboot.org/contributing/coding_style.html#headers-and-includes Also sort includes while on it. Change-Id: Ie62e4295ce735a6ca74fbe2499b41aab2e76d506 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70291 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-12-09soc/amd/mendocino: Enable LPC SPI DMAKarthikeyan Ramasubramanian
Enable LPC SPI DMA. This helps with ~20ms boot time improvement while loading various components synchronously. BUG=None TEST=Build Skyrim BIOS image and boot to OS. Observe a boot time improvement of ~20 ms. Before: Total Time: 1,503,032 After: Total Time: 1,485,536 Change-Id: I4dd57d46ae9bd664d57178d34b5beda872ed2cdb Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70383 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-08vc/amd/fsp/cezanne/FspmUpd: don't use pointers for usb_phy configurationFelix Held
The size of a pointer changes between a 32 and 64 bit coreboot build. In order to be able to use a 32 bit FSP in a 64 bit coreboot build, change the pointer in the UPDs to a uint32_t to always have a 32 bit field in the UPD for this. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I81f3a38344f91cecb4fe5431ed211834e5ed599c Reviewed-on: https://review.coreboot.org/c/coreboot/+/69897 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-08vc/amd/fsp/mendocino/FspmUpd: don't use pointers for usb_phy configFelix Held
The size of a pointer changes between a 32 and 64 bit coreboot build. In order to be able to use a 32 bit FSP in a 64 bit coreboot build, change the pointer in the UPDs to a uint32_t to always have a 32 bit field in the UPD for this. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I419fef73d2881e323487bc7fe641b2ac4041cb17 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70135 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-12-08soc/amd/common/acpi, mb/google/skyrim: Implement DTTS ProposalEricKY Cheng
DTTS indicated Dynamic Thermal Table Switching.The proposal would like to develop the schematic for switching 6 thermal table by lid status, machine body mode and temperature. After entering the OS, the thermal table would be table A. If the “Motion” or “Lid status change” is detected. The thermal table would switch to laptop mode or lid close mode. Once the higher environment temperatures are detected,the thermal table would switch to the corresponding power throttle table (B, D or F). Based on these table switching mechanisms, no matter how the end-user uses Chromebook,they could enjoy more humanized thermal designs. Release Over Over Release . Temp. Temp. Temp. Temp. . -------------------------------------------------------- . Desktop mode Table A Table B 50C 45C . Lid open (Default) . -------------------------------------------------------- . Desktop mode Table C Table D 55C 50C . Lid close . -------------------------------------------------------- . Laptop mode Table E Table F 45C 40C . -------------------------------------------------------- . On the proposal, the transmission rules are list below: 1. Table A is the default table after booting. 2. A, C, E (Release Temp) can switch to each other. 3. B, D, F (Over Temp) can switch to each other. 4. A and B, C and D, E and F can switch to each other. 5. If Lid open/close or mode switch event trigger, temperature release tables will translation to each other, temperature over tables will translation to each other.After that event trigger, EC will check the new temperature condition and decide if the temperature need to be trigger.For example, if table A will switch to table D, table A will switch to C with Lid close event, if temperature is over 55C, EC will trigger temperature to switch form table C to D. 6. EC will trigger 3 times body-detection events during power on boot without any body-mode and lid status change. For this case if the previous table label is on same group, we will based on the temperature to decide the table. For example, assume table A is current table. When the temperature reaches 50C, than the table is switched from A to B. The current table is B. When the temperature is downgrade below 45C, the table is switched form B to A. The same rule is for C and D, E and F. BRANCH=none BUG=b:232946420 TEST=emerge-skyrim coreboot Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com> Change-Id: I866e5e497e2936984e713029b5f0b6d54cbc9622 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68471 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
2022-12-08soc/amd/common/amdblocks/gpio: update amdblocks/gpio_defs.h includeFelix Held
Include <amdblocks/gpio_defs.h> instead of "gpio_defs.h", since gpio_defs.h is not only visible in a local scope, but also as <amdblocks/gpio_defs.h>. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iab3e5bb235a5b1bc995b6cf8710f0d8c1886142d Reviewed-on: https://review.coreboot.org/c/coreboot/+/70432 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-07soc/amd/common/block/acpi/ivrs: read IOAPIC IDs from hardwareFelix Held
TEST=IVRS table doesn't change on amd/mandolin Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5be04bc91425480992fcad12f8720738f9ca490e Reviewed-on: https://review.coreboot.org/c/coreboot/+/70357 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-06sb,soc/amd: Remove unused southbridge_io_trap_handler()Kyösti Mälkki
At the moment IO trap is not implemented for AMD platforms. Change-Id: Ib62ac4e4e418a8bab80c30dfb5183ecd8beb998d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70360 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-12-05soc/amd/common/block/include/gpio_defs.h: Fix documentationFred Reitberger
Fixing documentation of PAD_INT macro and replacing spaces with a tab to match the rest of the documentation. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I72a2578ce21dd10b3beb65c706440c3379f216d6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70281 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-30soc/amd/mendocino: Enhance DPTC_INPUT to support 13 DPTC thermal parametersEricKY Cheng
Expand DPTC_INPUT macro to supoort 13 DPTC thermal table parameters for dynamic table switching support. BRANCH=none BUG=b:232946420 TEST=emerge-skyrim coreboot Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com> Change-Id: I6d6a00f0eca0b0941860b9bc75da41d7a10d60e8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68649 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>