coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2017-06-27	soc/stoneyridge: Remove FCH PCIe support	Marshall Dawson
	Remove the pcie.c file. Historically PCIe lanes have been available from the Gfx and/or the FCH. The integrated FCH in this APU has no PCIe available. BUG=chrome-os-partner:62580062 Change-Id: Ie89383dadfaa57c5a6d185e74551ae50ac8d9778 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/20319 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-06-26	soc: Add AMD Stoney Ridge southbridge code	Marc Jones
	Copy the Hudson/Kern code from southbridge/amd/pi/hudson. This is the first of a series of patches to migrate Stoney Ridge support from cpu, northbridge, and southbridge to soc/ Changes: - add soc/amd/stoneyridge and soc/amd/common - remove all other Husdon versions - update include paths, etc - clean up Kconfig and Makefile - create chip.c to contain chip_ops Change-Id: Ib88a868e654ad127be70ecc506f6b90b784f8d1b Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>