| Age | Commit message (Expand) | Author |
|---|---|---|
| 2017-10-16 | soc/amd/stoneyridge: Check UART index | Marshall Dawson |
| 2017-10-03 | soc/amd/stoneyridge: Wait for UART to be ready | Marc Jones |
| 2017-08-14 | stoneyridge: Rename hudson to southbridge | Marc Jones |
| 2017-07-27 | soc/amd/common: Convert to C_ENVIRONMENT_BOOTBLOCK | Marshall Dawson |
| 2017-07-27 | soc/amd/stoneyridge: Convert 48Mhz enable to read/write32 | Marshall Dawson |
| 2017-07-27 | soc/amd/stoneyridge: Clarify BAR mask in SPI base | Marshall Dawson |
| 2017-06-27 | soc/amd/stoneyridge: Remove PCIe-PCI bridge | Marshall Dawson |
| 2017-06-27 | soc/amd/stoneyridge: Fix most checkpatch errors | Marshall Dawson |
| 2017-06-26 | soc: Add AMD Stoney Ridge southbridge code | Marc Jones |
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index : coreboot.git | |
| my copy of coreboot | User & |
| summaryrefslogtreecommitdiff |