| Age | Commit message (Expand) | Author |
|---|---|---|
| 2018-01-25 | soc/amd/stoneyridge: Add I2C devicetree support. | Justin TerAvest |
| 2017-11-20 | amd/stoneyridge: Fix SPD files and functions camel case | Marc Jones |
| 2017-11-10 | soc/amd/stoneyridge: Add UMA settings to devicetree | Aaron Durbin |
| 2017-11-10 | soc/amd/common: Add DRAM clear option to northbridge.c | Richard Spiegel |
| 2017-11-03 | amd/stoneyridge: Clarify SPD structure in chip.h | Marshall Dawson |
| 2017-10-17 | soc/amd/stoneyridge: clean up chip.h | Martin Roth |
| 2017-08-28 | soc/amd: Standardize guards on header files | Martin Roth |
| 2017-06-27 | soc/amd/stoneyridge: Fix most checkpatch errors | Marshall Dawson |
| 2017-06-26 | soc/amd/stoneyridge: Add northbridge support | Marc Jones |
| 2017-06-26 | soc: Add AMD Stoney Ridge southbridge code | Marc Jones |
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index : coreboot.git | |
| my copy of coreboot | User & |
| summaryrefslogtreecommitdiff |