coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2022-06-07	soc/amd/common/block/cpu/: Make ucode update more generic	Fred Reitberger
2022-04-14	soc/amd/sabrina: Allow to specify custom SPL File	Karthikeyan Ramasubramanian
2022-04-14	soc/amd/sabrina: Maintain a single copy of PSP Level2 entries	Karthikeyan Ramasubramanian
2022-04-01	soc/amd/sabrina/makefile: drop multilevel option in amdfwtool calls	Felix Held
2022-03-30	soc/amd/sabrina/makefile: use Sabrina as SoC name in amdfwtool call	Felix Held
2022-03-30	soc/amd/sabrina/makefile: drop PSP_S0I3_RESUME_VERSTAGE handling	Felix Held
2022-03-30	soc/amd/sabrina: Add espi_switch_to_spi1_pads	Raul E Rangel
2022-03-25	soc/amd/sabrina: update soft fuse bit 15 definition	Felix Held
2022-02-11	soc/amd/cezanne,picasso,sabrina: Fix incorrect values of CBFS amdfw position ...	Robert Zieba
2022-01-27	soc/amd/sabrina: drop PM_ESPI_CS_USE_DATA2 define and eSPI util code	Felix Held
2022-01-27	soc/amd/sabrina: drop CPPC code	Felix Held
2022-01-27	soc/amd/sabrina: drop graphics.c	Felix Held
2022-01-25	soc/amd/sabrina: add new SoC as copy of soc/amd/cezanne	Felix Held