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path: root/src/soc/amd/picasso
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2021-11-02psp_verstage: convert relative address in EFS2Kangheui Won
Addresses in AMD fw table with EFS gen2 are relative addresses, but PSP doesn't accept relative addresses in update_psp_bios_dir(). Check for EFS gen2 and convert them as needed. BUG=b:194263115 TEST=build and boot on guybrush and shuboz Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: I95813beba7278480e6640599fcf7445923259361 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58316 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-10-26cpu/x86: Introduce and use `CPU_X86_LAPIC`Felix Held
With using a Kconfig option to add the x86 LAPIC support code to the build, there's no need for adding the corresponding directory to subdirs in the CPU/SoC Makefile. Comparing which CPU/SoC Makefiles added (cpu/)x86/mtrr and (cpu/)x86/lapic before this and the corresponding MTRR code selection patch and having verified that all platforms added the MTRR code on that patch shows that soc/example/min86 and soc/intel/quark are the only platforms that don't end up selecting the LAPIC code. So for now the default value of CPU_X86_LAPIC is chosen as y which gets overridden to n in the Kconfig of the two SoCs mentioned above. Change-Id: I6f683ea7ba92c91117017ebc6ad063ec54902b0a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44228 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-10-26soc/*/Makefile: don't add cpu/x86/cacheFelix Held
No SoC uses the ramstage-only x86_enable_cache helper function to call enable_cache with some added port 0x80 and console output. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Angel Pons <th3fanbus@gmail.com> Change-Id: I7c5039e1341fd4089078ad7ffb2fe6584a94045c Reviewed-on: https://review.coreboot.org/c/coreboot/+/58547 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-10-25cpu,soc/amd/*/Makefile: don't add cpu/x86/pae a second timeFelix Held
Since cpu/x86/Makefile.inc already adds the pae sub-directory, there is no need to include it in the Makefile of a CPU or SoC, so remove it from those Makefiles. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I78368f7eb880fb64f511a2fa8c8acde222d0dca3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58546 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-10-25cpu,soc/x86: always include cpu/x86/mtrr on x86 CPUs/SoCsFelix Held
All x86-based CPUs and SoCs in the coreboot tree end up including the Makefile in cpu/x86/mtrr, so include this directly in the Makefile in cpu/x86 to add it for all x86 CPUs/SoCs. In the unlikely case that a new x86 CPU/SoC will be added, a CPU_X86_MTRR Kconfig option that is selected be default could be added and the new CPU/SoC without MTRR support can override this option that then will be used in the Makefile to guard adding the Makefile from the cpu/x86/mtrr sub-directory. In cpu/intel all models except model 2065X and 206AX are selcted by a socket and rely on the socket's Makefile.inc to add x86/mtrr to the subdirs, so those models don't add x86/mtrr themselves. The Intel Broadwell SoC selects CPU_INTEL_HASWELL and which added x86/mtrr to the subdirs. The Intel Xeon SP SoC directory contains two sub-folders for different versions or generations which both add x86/mtrr to the subdirs in their Makefiles. Change-Id: I743eaac99a85a5c712241ba48a320243c5a51f76 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44230 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-22soc/amd/cezanne,picasso/chipset.cb: drop LAPIC deviceFelix Held
After adding code to handle the case of missing the link/bus on the CPU cluster device in mp_cpu_bus_init, there's no need to have the LAPIC device in the devicetree any more. TEST=Mandolin still boots successfully. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Icfc4fb61b373129f3bf4f4de09c38076a8f66733 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58510 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-22arch/x86/ioapic: Select IOAPIC with SMPKyösti Mälkki
For coreboot proper, I/O APIC programming is not really required, except for the APIC ID field. We generally do not guard the related set_ioapic_id() or setup_ioapic() calls with CONFIG(IOAPIC). In practice it's something one cannot leave unselected, but maintain the Kconfig for the time being. Change-Id: I6e83efafcf6e81d1dfd433fab1e89024d984cc1f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55291 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-22cpu/x86/mp_init: move printing of failure message into mp_init_with_smmFelix Held
Each CPU/SoC checks the return value of the mp_init_with_smm and prints the same error message if it wasn't successful, so move this check and printk to mp_init_with_smm. For this the original mp_init_with_smm function gets renamed to do_mp_init_with_smm and a new mp_init_with_smm function is created which then calls do_mp_init_with_smm, prints the error if it didn't return CB_SUCCESS and passes the return value of do_mp_init_with_smm to its caller. Since no CPU/SoC code handles a mp_init_with_smm failure apart from printing a message, also add a comment at the mp_init_with_smm call sites that the code might want to handle a failure. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I181602723c204f3e43eb43302921adf7a88c81ed Reviewed-on: https://review.coreboot.org/c/coreboot/+/58498 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-21cpu/x86/mp_init: use cb_err as mp_init_with_smm return typeFelix Held
Using cb_err as return type clarifies the meaning of the different return values. This patch also adds the types.h include that provides the definition of the cb_err enum and checks the return value of mp_init_with_smm against the enum values instead of either checking if it's non-zero or less than zero to handle the error case. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ibcd4a9a63cc87fe176ba885ced0f00832587d492 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58491 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-20psp_verstage: remove psp_ef_table structKangheui Won
psp_efs.h now has embedded_firmware struct which is copied from amdfwtool. Remove psp_ef_table from psp_verstage and use it instead to remove duplicates. TEST=boot on zork and guybrush Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: Ia362445cb7fc565b2d963f264461d833dc0338d0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58411 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-10-19acpi/acpigen: Constify CST functions' pointersAngel Pons
The `acpigen_write_CST_package` and `acpigen_write_CST_package_entry` functions don't modify the provided C-state information. So, make the pointer parameters read-only to enforce this. Also constify arguments where possible. Change-Id: I9e18d82ee6c16e4435b8fad6d467e58c33194cf4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58391 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-10-15soc/amd: make configure_espi_with_mb_hook call conditionalFelix Held
If a system doesn't use eSPI or has the eSPI interface already configured in verstage on PSP, not calling configure_espi_with_mb_hook from fch_pre_init makes it a bit more obvious that the eSPI interface initialization will be skipped. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia77b83d56a5dab1bac6cfbbd92d33aa60a9e8b89 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58339 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-15soc/amd/common/include/espi: rename configure_espiFelix Held
Rename configure_espi to configure_espi_with_mb_hook to clarify that this function will call into the mb_set_up_early_espi function in the mainboard-specific code if it exists. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5d0f099288b0100242629c736dd69a8add977b5b Reviewed-on: https://review.coreboot.org/c/coreboot/+/58338 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-15soc/amd/common/block/i2c: implement proper read_resourceFelix Held
Before this patch the reservation of the MMIO region of the I2C controllers was done in the LPC controller PCI device despite the I2C controllers already being devices in the devicetree. This patch implements this functionality as read_resources function of the I2C device instead. This will only reserve the memory when the I2C devices are enabled in devicetree which is a change from the previous behavior. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I67c853df3be2f593ecfa113ae2f74e5df7cf74e0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58307 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-15soc/amd/cezanne,picasso/uart: implement read_resourceFelix Held
Implement the read_resources function for the UART devices so that the resource allocator knows about their fixed MMIO resources when enabled. TEST=UART still works on Mandolin. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4ffddee3f5f4281aca98ddfcefa639dfb7a38dae Reviewed-on: https://review.coreboot.org/c/coreboot/+/58306 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-13soc/amd/common/block/espi_util: Refactor eSPI SetupKarthikeyan Ramasubramanian
eSPI is setup in two different locations in bootblock depending on early port80 routing configuration. Also eSPI is setup in PSP, if verified boot starts before bootblock. Consolidate all the scenarios by initializating eSPI very early in fch_pre_init if verified boot starts after bootblock and eSPI is enabled. BUG=None TEST=Build and boot to OS in Guybrush. Perform S5->S0, G3->S0, warm reset and suspend/resume cycles for 50 iterations each. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: Icfeba17dae0a964c9ca73686e29c18d965589934 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58114 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-13soc/amd/*: Enable ACPIMMIO decode first in fch_pre_initFelix Held
Since the GPIO mux/control MMIO regions are within the ACPIMMIO region, we need to call enable_acpimmio_decode_pm04 here first so that accessing the GPIO registers will work. BUG=None TEST=Build and boot to OS in Guybrush. Change-Id: I4bc076261c72cf999a5f2464b74cff6bf694d473 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57782 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-05src/soc to src/superio: Fix spelling errorsMartin Roth
These issues were found and fixed by codespell, a useful tool for finding spelling errors. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Ieafbc93e49fcef198ac6e31fc8a3b708c395e08e Reviewed-on: https://review.coreboot.org/c/coreboot/+/58082 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-23soc/amd/common/blocks/include: rename gpio_banks.h to gpio.hFelix Held
This brings the AMD SoC GPIO code in line with the Intel SoC code and removes the not really needed suffix. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie2dbec81dfe503869beb2872b01a7475e2b88b33 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57842 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-23soc/amd: rename program_gpios to gpio_configure_padsFelix Held
Use the same function name as in soc/intel for this functionality. This also brings the function name more in line with the extended version of this function gpio_configure_pads_with_override which additionally supports passing a GPIO override configuration. This might cause some pain for out-of-tree boards, but at some point this should be made more consistent, so I don't see a too strong reason not to do this. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I88852e040f79861ce7d190bf2203f9e0ce156690 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57837 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-21soc/amd/picasso/fsp_m_params: use DEV_PTR to check if device is enabledFelix Held
The aliases are defined in the chipset devicetree, so the device pointers will be available for all boards using this SoC. TEST=None Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id4c921575e978bb29e61f35e78ff2a1711acf06a Reviewed-on: https://review.coreboot.org/c/coreboot/+/57780 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-17soc/amd/picasso/Kconfig: increase FSP_M_SIZEFelix Held
When using a debug build of the FSP, the FSP-M binary is larger than the memory region we have allocated for it, so increase the size to make the binary of the debug build fit in there. Also adjust the VERSTAGE_ADDR so that it starts right after the the FSP-M memory region. TEST=coreboot builds now successfully when using a debug version of the FSP Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib64806bcf948d5ed4bcf8e1f50004091f125dc7e Reviewed-on: https://review.coreboot.org/c/coreboot/+/57718 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-16soc/amd/picasso/agesa_acpi: Add missing include 'arch/cpu.h'Raul E Rangel
Needed for cpuid_ext. BUG=b:179699789 TEST=build morphius Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ib3a132bea06443ee4c1501b1c746400c541fd805 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57618 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-09soc/amd/common/block/include/i2c: introduce I2C_RESET_SCL_PIN macroFelix Held
Add and use the I2C_RESET_SCL_PIN macro for populating the i2c_scl_pins array that is used for the sb_reset_i2c_peripherals call to bring the I2C buses into a defined state. TEST=Timeless build results in identical image for Mandolin. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ifedc09d0bf745545fa0510df7d5037f02b9012a6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57479 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-08soc/amd/*/bootblock,early_fch: rework i2c_scl_pins configurationFelix Held
drive_scl in soc/amd/common/block/i2c/i2c.c writes the raw GPIO MMIO configuration register and drives it as output, so don't initially configure the GPIO as input with no pull up/down. This is a preparation to use the common AMD GPIO access functions instead of the raw register accesses, since the gpio_set function only sets the output value, but doesn't reconfigure the direction. Using gpio_output there instead would reconfigure the direction as well, but would result in doubling the number of MMIO accesses, so just configure the GPIOs correctly right away to avoid that. TEST=The waveform on the SCL pin of I2C3 on a barla/careena Chromebook looks exactly the same as before during the reset_i2c_peripherals call. This was probed at the SCL pad of the unpopulated I2C level shifter on the side that is connected to the SoC. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8e94afe0c755a02abcc722d5094e220d8781f8f5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56807 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-04soc/amd/picasso: select ADD_FSP_BINARIES if USE_AMD_BLOBS is selectedFelix Held
Since the FSP binaries for Picasso are present in the amd_blobs repo, select the ADD_FSP_BINARIES option if the Kconfig option to check out that repo is set. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I9a8571730cf271ad5e113e5df87700882b3c5475 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57348 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-08-31soc/amd/*/include/soc/gpio: remove GPIO_2_EVENTFelix Held
commit de7262f82cdc1a7c868dbc9ca41e186e885eb2ba (soc/amd: remove special GPIO_2 override soc_gpio_hook) removed the workaround that needed those definitions, so remove the now unused GPIO_2_EVENT definitions. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3f3e3061eade0e0cd25e2263451ccf6cefdc4ea4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56812 Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-30soc/amd: Show SPI settings in bootblockMartin Roth
BUG=b:194919326 TEST=See SPI settings in bootblock Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I8ee8981986990240b09414cde8b84d9b109cb5b2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56961 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-08-19acpi: Fill fadt->century based on KconfigNico Huber
Change-Id: I916f19e022633b316fbc0c6bf38bbd58228412be Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56218 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lance Zhao Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-08-05soc/amd/picasso: Move IVRS generation code to commonJason Glenesk
Move IVRS acpi table generation code to common, so that it can be shared by other programs. BUG=b:190515051 TEST=Build picasso coreboot image. Compare IVRS tables before/after change. Change-Id: Icd5fec3a9d66e8301e267312020e726d9bc1aa70 Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56450 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-07-24soc/amd/*/chip.h: Correct PSPP Enum ValueMatt Papageorge
It appears the pspp_policy enum is not the same as the FSP definition currently being used. This means that the incorrect PSPP value setting would get read by FSP. For Zork programs this meant we actually were setting links as DXIO_PSPP_BALANCED instead of DXIO_PSPP_POWERSAVE. This change adds DXIO_PSPP_DISABLED as the first enum value to properly match the FSP definition and adjusts non AMD Customer Reference Boards that reference the enum to still send the same value even though it has now change definitions. If we actually want DXIO_PSPP_POWERSAVE for those boards that can be adjusted in a future change. BUG=b:193495634 TEST=Boot to OS with Majolica and Guybrush and run 10G iperf on wifi with other server on local network. Change-Id: I287b6d3168697793a2ae8d8e68b4ec824f2ca5ef Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56463 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2021-07-23soc/amd/picasso/fch: change sb prefix of sb_clk_output_48Mhz to fchFelix Held
Picasso has an integrated FCH and no south bridge, so change the sb prefix to fch. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I82aed68104ea9570827646c818e100bd7e04d1af Reviewed-on: https://review.coreboot.org/c/coreboot/+/56526 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-23soc/amd/picasso/fch: make sb_clk_output_48Mhz staticFelix Held
sb_clk_output_48Mhz is only used in fch.c where it is also implemented, so no need to have it visible outside of that compilation unit. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I2b0d10ff26bdf54ea791aa66bf400578466d54cf Reviewed-on: https://review.coreboot.org/c/coreboot/+/56525 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-21soc/amd/cezanne: enable crypto in psp_verstageKangheui Won
Enable RSA and SHA for cezanne since support has been added to the PSP. Also picasso and cezanne have different enums definitions for hash algorithm, so split that out into chipset.c. BUG=b:187906425 TEST=boot guybrush, check cbmem -t and the logs Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: I725b0cac801ac0429f362a83aa58a8b9de158550 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55833 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-07-20soc/amd/picasso/makefile: order source files alphabeticallyFelix Held
Change-Id: I6eb0881ab05730b094caef2a9258c4d4d827195b Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56427 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-07-19soc/amd/{cezanne,picasso}: Escape PSP_VERSTAGE_FILE defaultRaul E Rangel
If we don't escape the $ then the actual $(obj) path will be written into the .config file. With this change `$(obj)` is written into the .config file. The Makefile then does: PSP_VERSTAGE_FILE=$(call strip_quotes,$(CONFIG_PSP_VERSTAGE_FILE)) Since this is a recursive assignment the $(obj) will be expanded at that point. This change makes it easier to compare full .config files. BUG=none TEST=Build ezkinil Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ic961df148d3f22585f3441d75c3f2454329c678a Reviewed-on: https://review.coreboot.org/c/coreboot/+/56395 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2021-07-15soc/amd/*/mca: factor out common MCA/MCAX check & print functionalityFelix Held
For Cezanne stubs are added for the functions that the SoC-specific code needs to provide. Since the mca_is_valid_bank stub on Cezanne always returns false, the checks get skipped for it at the moment. The actual functionality will be added in a later patch. Change-Id: Ic31e9b1ca7f8fac0721c95935c79150d7f774aa4 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56290 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-07-15soc/amd/picasso/mca: factor out mca_has_expected_bank_countFelix Held
To factor out the rest of the common MCAX code, mca_bank_name[] may only be accessed by accessor functions, so implement this for the last place that still accessed mca_bank_name[] directly. Change-Id: Ic6548d3ceeb9c00ad344fc0bb3d97893e17a43a9 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56294 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-15soc/amd/*/mca: factor out BERT entry generation to soc/amd/commonFelix Held
Change-Id: I960a2f384f11e4aa5aa2eb0645b6046f9f2f8847 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56283 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-14soc/amd/picasso/mca: add missing types.h includeFelix Held
Change-Id: I67a88298c19657a5049ab69799be887555ca7240 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56282 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-07-14soc/amd: factor out check_mca to common codeFelix Held
Change-Id: I139d1fe41bad5213da8890c2867f275b6847e3e1 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56281 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-14soc/amd: move check_mca prototype to soc/amd/common/blocks/includeFelix Held
Change-Id: Ia489dbfba59c334cf29f96a4000cef73b9b797d4 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56279 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-14soc/amd/picasso: implement and use mca_get_bank_nameFelix Held
Change-Id: I42abff5efcd7c85d2932a7aaacc736d0376cfaa0 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56276 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-07-14soc/amd/picasso: implement and use mca_is_valid_bankFelix Held
In mca_check_all_banks only check valid MCA banks for errors. This aligns the Picasso code a bit more with the Stoneyridge code base which will be updated in a follow-up patch. This is a preparation for commonizing the MCA(X) handing in the soc/amd sub-tree. Change-Id: I0c7f3066afd220e6b8bf8308a321189d7a2679f6 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56275 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-14soc/amd/picasso: check length of mca_bank_name arrayFelix Held
The length of mca_bank_name should match the return value of mca_get_bank_count which gets the number of MCA banks from an MSR. TEST=No error message on serial console on amd/mandolin Change-Id: Ibdad51a7ef27266e110dfbb43188361952618342 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56274 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-14soc/amd/picasso: add missing banks to mca_bank_name arrayFelix Held
Also use array indices for the initialization. TEST=Checked with the public Picasso PPR #55570-B1 Rev 3.16 Change-Id: I10a65210da73e64b67d613609fcc0f9a245a81fb Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56273 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-14soc/amd/cezanne: Move APOB update into ramstageRaul E Rangel
There is no technical reason this needs to be done in romstage. Moving it into ramstage allow us (in future CLs) to use threads to pre-load the apob from SPI. BUG=b:179699789 TEST=Boot and Ezkinil and Guybrush and verify APOB update still work Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I960437ff4400645de5a3e7447fcdbc52de85943e Reviewed-on: https://review.coreboot.org/c/coreboot/+/56227 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-07-14soc/amd/picasso/mca: use mca_clear_status()Felix Held
Since we can use both the old MCA registers and the new MCAX registers to access the MCA status registers, we can use the common mca_clear_status function here. Change-Id: I9ddcc119eca2659361b1496fd7ffe124fb323d26 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56260 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-07-14soc/amd/picasso,stoneyridge/mca: factor out mca_check_all_banksFelix Held
Change-Id: I5496fd27f5c56d35ab95a5e02ea313b5b5536668 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56241 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-14soc/amd/picasso,stoneyridge/mca: factor out mca_clear_errorsFelix Held
Change-Id: Id7a716a2598a6a7bea2d2d56898ea6329b5a3bec Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56240 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-14soc/amd/picasso,stoneyridge/mca: factor out mca_print_error()Felix Held
Change-Id: I7cd05a389c34c2e5f3d0ab4cd06d60a7e3e5cad9 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56239 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-14soc/amd/picasso,stoneyridge/mca: use unsigned int for MCA bank numberFelix Held
Change-Id: Ib31075fd615eaa8492ce0179b3b21317554f1c80 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56238 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-14soc/amd/picasso,stoneyridge/mca: clean up mca_bank structFelix Held
Only the fields bank and sts from the mca_bank struct were used outside a local scope, so remove the rest. Also rename the struct that now only contains the bank number and the status MSR content to mca_bank_status. Change-Id: I925347dff950ac2bd021635ca988c02fba48df7f Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56237 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-14soc/amd/picasso,stoneyridge/mca: mark num_banks as constantFelix Held
Change-Id: I23aa4d36d4e6d4c7ed66800c2e7963c4ed03c393 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56236 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-14src: Use initial_lapicid() instead of open coding itArthur Heymans
Since initial_lapicid() returns an unsigned int, change the type of the local variables the return value gets assigned to to unsigned int as well if applicable. Also change the printk format strings for printing the variable's contents to %u where it was %d before. Change-Id: I289015b81b2a9d915c4cab9b0544fc19b85df7a3 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55063 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-12soc/amd/*/mca: use mca_get_bank_count()Felix Held
Use the common mca_get_bank_count function instead of open-coding the functionality to get the MCA bank number. Also re-type the num_banks variable from signed in to unsigned int, since the number of MCA bank is always positive. Change-Id: I126767cf9ad468cab6d6537dd73e9b2dc377b5c4 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56185 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-07-12soc/amd/picasso,stoneyridge/mca: remove unneeded line breakFelix Held
Change-Id: Ib74ff1d585f8ef54960e6a1eafd5a280907f8675 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56180 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-06soc/amd/picasso: Allow end range entry for max device ID in IVRSAamir Bohra
Allow hot plug devices to subscribe to IOMMU services. Currently the IOMMU end range is limited to device B:0 D:1f F:6. This prevents the devices on bus 1 and higher to subscribe to IOMMU services. As per AMD IOMMU spec v3 section 5.2.2.1 all possible device IDs must be defined, whether the device ID is actually populated or not. Device entries are used to report ranges when hot-plug and SR-IOV devices are possible. With this change the hot plug devices can now bind to IOMMU services (as tested on kernel v5.4), and below errors are not seen in dmesg. AMD-Vi: Event logged [IO_PAGE_FAULT device=04:00.3 domain=0x0000] AMD-Vi: Event logged [IO_PAGE_FAULT device=05:00.0 domain=0x0000] AMD-Vi: Event logged [IO_PAGE_FAULT device=04:00.4 domain=0x0000] TEST= Verify dGPU can enumerate on hotplug. No IO page fault errors seen. The hot plug devices can successfully bind to IOMMU services in kernel. Signed-off-by: Aamir Bohra <aamirbohra@gmail.com> Change-Id: I256c0f8032662674a4d75746de49c250e341c579 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55816 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Reviewed-by: ritul guru <ritul.bits@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-02src: Introduce `ARCH_ALL_STAGES_X86`Angel Pons
Introduce the `ARCH_ALL_STAGES_X86` Kconfig symbol to automatically select the per-stage arch options. Subsequent commits will leverage this to allow choosing between 32-bit and 64-bit coreboot where all stages are x86. AMD Picasso and AMD Cezanne are the only exceptions to this rule: they disable `ARCH_ALL_STAGES_X86` and explicitly set the per-stage arch options accordingly. Change-Id: Ia2ddbae8c0dfb5301352d725032f6ebd370428c9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55759 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-06-30src: Move `select ARCH_X86` to platformsAngel Pons
To generalise the choice of 32-bit or 64-bit coreboot on x86 hardware, have platforms select `ARCH_X86` directly instead of through per-stage Kconfig options, effectively reversing the dependency order. Change-Id: If15436817ba664398055e9efc6c7c656de3bf3e4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55758 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-06-18soc/amd/picasso,stoneyridge/acpi: use defines for MADT parametersFelix Held
Using existing defines instead of magic values improves readability of the code. Also add comments to the MADT IRQ overrides to make it clearer what those actually do. TEST=Timeless build results in identical binary for amd/gardenia (Stoneyridge), amd/mandolin (Picasso) and amd/majolica (Cezanne) Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I224ffbe8eb65bcdd5fc70c0ff8b15d55b3f6be01 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55613 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-17soc/amd/picasso: introduce and use devicetree aliases for UART0-3Felix Held
Since the default state of the MMIO UART devices in the chipset devicetree is off, the mainboard devicetree entries that disable MMIO UART devices are removed. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I913a587802020ce4e182b48632cdde1104c2a6e6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55545 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-16soc/amd/picasso/Kconfig: fix CONSOLE_UART_BASE_ADDRESS for SoC UART2Felix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6deb2a4c632d39112dcce71f076742a1b62ee89b Reviewed-on: https://review.coreboot.org/c/coreboot/+/55546 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-16soc/amd/picasso: introduce and use devicetree aliases for I2C2&I2C3Felix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I06102f4fcc3bf9de332c71a52c632241b95cde19 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55543 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-16soc/amd/cezanne,picasso/include/soc/iomap: reflow I2C_DEVICE_COUNTFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I7edae2142120dec9e11ef823b561401b7e0bc208 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55535 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-06-16soc/amd/picasso/acpi/sb_fch: use AOAC offset definesFelix Held
Replace the magic numbers with the existing defines. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I2d98ea8c5bb0e487c7eef0b0a1cdada9cb04df4a Reviewed-on: https://review.coreboot.org/c/coreboot/+/55532 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-06-16soc/amd/picasso: factor out AOAC offset definesFelix Held
Factoring out those defines allows using them easily in the ACPI code without having to use preprocessor macros. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I99cb03de8782a0eeeb505f567b982099b0e8a18d Reviewed-on: https://review.coreboot.org/c/coreboot/+/55531 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-06-16soc/amd/cezanne,picasso: add AOAC offset define for the eMMC controllerFelix Held
BUG=b:184978118 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I03554a151aa6a6d9e15d74c63cd02239b788808a Reviewed-on: https://review.coreboot.org/c/coreboot/+/55530 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-06-14soc/amd/{cezanne,picasso}: Add TS_START_ROMSTAGERaul E Rangel
BUG=b:179092979 TEST=boot guybrush and see romstage tag 14:finished loading romstage 2,683,151 (10,079) 1:start of romstage 2,683,159 (8) 970:<unknown> 2,683,386 (227) 15:starting LZMA decompress (ignore for x86) 2,683,391 (5) 16:finished LZMA decompress (ignore for x86) 2,717,867 (34,476) Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ib8b3fe909140e05a89b74df526bf4f81799ad915 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55398 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-13soc/amd/picasso: Move Type 17 DMI generation to commonNikolai Vyssotski
Move dmi.c code to common/fsp to be shared among different SOCs. BUG=b:184124605 Change-Id: I46071556bbbbf6435d9e3724bba19e102bd02535 Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52746 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-06-11cpu/x86/lapic: Replace LOCAL_APIC_ADDR referencesKyösti Mälkki
Note that there are assumptions about LAPIC MMIO location in both AMD and Intel sources in coreboot proper. Change-Id: I2c668f5f9b93d170351c00d77d003c230900e0b4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55194 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-08soc/amd: factor out acpi_soc_get_bert_region to amd/commonFelix Held
This also adds BERT table gerenation support for Cezanne, but since the functionality to populate the BERT memory region isn't implemented yet, this won't result in a BERT table being generated on Cezanne, since bert_generate_ssdt will always return false there. TEST=BERT ACPI table generation still works on AMD/Mandolin Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I69b4a9a7432041e1f4902436fa4e6dee5332dbd2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55056 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-06-08soc/amd/picasso/agesa_acpi: add BERT supportFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I14577e80e722cb5ccf344a4520cf3adde669fc5e Reviewed-on: https://review.coreboot.org/c/coreboot/+/54149 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-06-07cpu/x86: Default to PARALLEL_MP selectedKyösti Mälkki
Change-Id: I9833c4f6c43b3e67f95bd465c42d7a5036dff914 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55196 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-06-02soc/amd/picasso: remove warm reset flag codeFelix Held
Since the MCA(X) registers have defined values on the cold boot path, the is_warm_reset check can be dropped. Also the warm reset bit in the NCP_ERR register doesn't behave as the PPR [1] suggested; no matter if something was written to the register or the machine went through a warm reset cycle, the NCP_WARM_BOOT bit never got set. [1] checked with PPR for AMD Family 17h Models 11h,18h B1 (RV,PCO) #55570 Rev 3.15 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4e6df98ffd5d15ca204c9847a76c19c753726737 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55059 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-06-01soc/amd/picasso: introduce and use chipset device treeFelix Held
The chipset devicetree only has the essential PCIe devices enabled that are needed for the SoC code to work. It also defines aliases for all PCIe devices that can be used to reference the devices in the mainboard- specific devicetrees and devicetree overrides. To make the change easier to review that part will be done in a follow-up patch. Despite missing in the PPR, device pci 18.7 exists on Picasso. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6b7c3fd32579a23539594672593a243172c161c7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50626 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-05-28soc/amd/picasso: fix MCACHE on psp_verstage RO bootKangheui Won
On RW boot path psp_verstage call cbfs_map which calls chain of _cbfs_alloc, cbfs_boot_lookup and cbfs_get_boot_device. Then cbfs_get_boot_device initializes MCACHE which is used later. However on RO boot path psp_verstage doesn't try to find anything in the CBFS which results RO MCACHE not to be initialized. Add cbfs_get_boot_device(true) to explicitly initialize MCACHE on recovery boot. BUG=b:177091575 BRANCH=none TEST=build and boot jelboz Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: I6c4b522fef5a4affd215faa122bdf6b53190cf3d Reviewed-on: https://review.coreboot.org/c/coreboot/+/54711 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-27soc/amd/picasso: add devicetree setting for PSPP policyFelix Held
Since the default for the corresponding UPD of the Picasso FSP is DXIO_PSPP_POWERSAVE and the devicetree default is DXIO_PSPP_PERFORMANCE, add a deviectree setting for each board that's using the Picasso SoC code to not change the setting for the existing boards. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0008ebb0c0f339ed3bdf24ab95a20aa83d5be2c9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54934 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-05-26soc/amd/picasso/mca: use MCAX registers instead of legacy MCAFelix Held
This patch also adds the additional 10 MCAX registers to the BERT MSR error record. BUG=b:186038401 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I31912d3b3e77e905f64b6143042f5e7f73db7407 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52616 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-05-22soc/amd: reduce MCACHE size with psp_verstageKangheui Won
The default of CBFS_MCACHE_SIZE is increased to 0x4000 in CB:54146 but we have limited space on the PSP thus cannot afford it. BUG=b:177091575 BRANCH=none Signed-off-by: Kangheui Won <khwon@chrmoium.org> Change-Id: I94dd782ae00d0b18ad6dd2fc061e4318bda88579 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54710 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-05-22soc/amd/cezanne,picasso/reset: use byte I/O read for NCP_ERRFelix Held
NCP_ERR is a 1 byte register in I/O-space, so use inb and not inw. The variable the result gets assigned to is also a uint8_t. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I9fd8c139004111d6227c0316ba2a8b0281541654 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54736 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-05-21soc/amd/cezanne,common,picasso: use BERT region reserved by FSP driverFelix Held
commit ce0e2a014009390c4527e064efb59260ef4d3a3b (drivers/intel/fsp2_0: use FSP to allocate APEI BERT memory region) adds a mechanism to reserve the BERT region inside the coreboot code, so we can get rid of the workaround to reserve it in the FSP and return the location in a HOB. mcfg->bert_size defaults to 0 which makes the FSP not generate the corresponding HOB, but that field is planned to be removed at least on Cezanne, so don't explicitly set it to 0. BUG=b:169934025 TEST=BERT table that gets generated in a follow-up patch for Picasso points to expected BERT region and Linux is able to access, decode and display it. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iaca89b47793bf9982181560f026459a18e7db134 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52584 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-19soc/amd/picasso: move gpp_clk_req_setting definition to chip.hFelix Held
Since this enum is only used for the devicetree settings and not for the hardware itself, move it from the southbridge header to the chip one. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0907fc5cba9315fec5fabff67d279c6d95d1c9f0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54684 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-16soc/amd/*/Makefile.inc: Strip the quotesZheng Bao
PSP_SOFTFUSE_BITS used to be like this: 15 0 29 "28 6" It causes internal shell report error: /bin/sh: -c: line 0: unexpected EOF while looking for matching `"' /bin/sh: -c: line 1: syntax error: unexpected end of file /bin/sh: -c: line 0: unexpected EOF while looking for matching `"' /bin/sh: -c: line 1: syntax error: unexpected end of file Change-Id: I716f19d37fb57b9ef3fc7259c6dcca7d21022d32 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54278 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-05-13soc/amd: factor out acpigen_write_alib_dptc to common codeFelix Held
Also drop unneeded intermediate cast to void * before casting the address of the struct dptc_input type variables to uint8_t *. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie1e2aa1ec728a4e16d3a587d7400cdfc8962f443 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54077 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-05-12soc/amd/{common,picasso}: Use common PCIE_GPP_DRIVER driverRaul E Rangel
This will change the names of the GPP bridges, but this ok since there is no hand written ASL that references these names. BUG=b:184766519 TEST=Boot picasso and dump ACPI Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ic09200156e8a37bd1a29ca95a17c8f8ae2b92bd3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54028 Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-11soc/amd/picasso: Disable CBFS MCACHE againRaul E Rangel
This is still causing boot errors on zork: coreboot-4.13-3659-g269e03d5c42f Fri May 7 22:03:11 UTC 2021 bootblock starting (log level: 8)... Family_Model: 00820f01 PSP boot mode: Development Silicon level: Pre-Production Set power off after power failure. PMxC0 STATUS: 0x800 BIT11 I2C bus 3 version 0x3132322a DW I2C bus 3 at 0xfedc5000 (400 KHz) FMAP: area COREBOOT found @ 875000 (7909376 bytes) ASSERTION ERROR: file 'src/commonlib/bsd/cbfs_mcache.c', line 106 BUG=b:177323348 TEST=Boot ezkinil to OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I68b4b73670e750207414f0d85ff96f21481be8ce Reviewed-on: https://review.coreboot.org/c/coreboot/+/53933 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-10soc/amd/picasso: move acpigen_dptc_call_alib to new common alibFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib0f7da12429b6278d1e4bc5d6650c7ee0f3b5209 Reviewed-on: https://review.coreboot.org/c/coreboot/+/53940 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-05-10psp_verstage: differentiate bios entryKangheui Won
AMDFW tool stores bios dir entry to bios1_entry in picasso but bios3_entry in cezanne. Separate getting bios_dir_addr into a function and implement it on each platforms. Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: Ie18ed7979a04319c074b9b251130d419dc7f22dc Reviewed-on: https://review.coreboot.org/c/coreboot/+/52964 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-10psp_verstage: move platform-specific code to chipset.cKangheui Won
Move all platform-specific code except direct svc calls to chipset.c. There will be differences between each platforms and we can't put everything into svc.c. TEST=build firmware for zork Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: Ie7a71d1632800072a17c26591e13e09e0269cf75 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52963 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-09soc/amd/picasso/pci_gpp: Switch to using acpigen_write_pci_GNB_PRTRaul E Rangel
We can now delete the picasso specific version. BUG=b:184766519 TEST=Build zork and verify SSDT has not changed Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ic79014e83c9ff63cc7a6757b16764ae23b36984f Reviewed-on: https://review.coreboot.org/c/coreboot/+/53935 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-09soc/amd/{picasso,common/blocks/pci}: Move populate_pirq_dataRaul E Rangel
The method now dynamically allocates the pirq structure and uses the get_pci_routing_table method. BUG=b:184766519 TEST=Build guybrush and verify picasso SSDT has not changed. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I297fc3ca7227fb4794ac70bd046ce2f93da8b869 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52913 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-05-09soc/amd/picasso: Migrate to struct pci_routing_infoRaul E Rangel
This allows us to use the common get_pci_routing_info and pci_calculate_irq. The IRQ field in the struct was also filled in from the PPR. BUG=b:184766519 TEST=Boot ezkinil and verify SSDT table is identical. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I16d90d8c89bfcf48878c0741154290ebc52a4120 Reviewed-on: https://review.coreboot.org/c/coreboot/+/53923 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-08soc/amd/picasso/acpi/cpu: move WAL1 method that calls ALIB to commonFelix Held
TEST=Mandolin still boots into Linux and there's no ACPI warning in dmesg. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I7e6d38ebeae5e55a4a65930b989838532ab9c446 Reviewed-on: https://review.coreboot.org/c/coreboot/+/53920 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-08soc/amd/picasso,common: move ALIB DPTC parameter struct to common codeFelix Held
Also add an alib_ prefix to avoid possible name collisions. TEST=Timeless build for Mandolin results in identical binary. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib0f220a4cde6da764bb8bc589b5f44ae16496bd7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/53918 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-08soc/amd/picasso,common: move ALIB DPTC IDs to common codeFelix Held
These parameter IDs are defined in the AGESA Interface specification #55483. This patch also adds a ALIB_DPTC_ prefix to the IDs and makes the names more consistent. TEST=Timeless build for Mandolin results in identical binary. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I75e0504f6274ad50c53faa8fcbde4d6821d85a04 Reviewed-on: https://review.coreboot.org/c/coreboot/+/53917 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-08soc/amd/picasso/root_complex: move DPTC_TOTAL_UPDATE_PARAMS out of enumFelix Held
The other enum entries are control IDs for the ALIB_FUNCTION_DYNAMIC_POWER_THERMAL_CONFIG ALIB function while DPTC_TOTAL_UPDATE_PARAMS is the total number of configuration settings that will get passed as parameter in the ALIB call, so it shouldn't be part of that enum. TEST=Timeless build for Mandolin results in identical binary. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0cb9e9d2ba579a74d916011b4ead71cc86d69a24 Reviewed-on: https://review.coreboot.org/c/coreboot/+/53916 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-08soc/amd: factor out ACPI ALIB function numbers to common codeFelix Held
The ACPI ALIB function numbers are defined in the AMD Generic Encapsulated Software Architecture (AGESA™) Interface Specification (document #55483). TEST=Timeless build stays the same for Mandolin (Picasso) and Gardenia (Stoneyridge). Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I290ef0db32c65ebb2bbbe4f65db4df772b884161 Reviewed-on: https://review.coreboot.org/c/coreboot/+/53915 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-06soc/amd/{common/picasso}: Move pci_int.aslRaul E Rangel
We can share this with cezanne. BUG=b:184766519 TEST=Build picasso Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: If746d55345f6b7c828376b64adc5532d20413f68 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52916 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-06soc/amd/{picasso/common}: Move populate_pirq_data prototype to commonRaul E Rangel
This method signature will also be used by cezanne, so move it to common. BUG=b:184766519 TEST=Build picasso Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I421bdad51776278f83148174e6f72bdc38249e54 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52912 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-20 17:07:43 +0000