coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2021-02-02	soc/amd/picasso/pcie_gpe: use PICM instead of PMOD in APCI code	Felix Held
	commit 3f2467032e3e40cd456d2d9fe5120a60283784aa changed this in the APCI code itself, but the change in the ACPI byte code generation in pcie_gpp.c was missed and this patch fixes that. TEST=Fixes the regression on Mandolin. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I60de29581296101947336f70343d6206af97e307 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50207 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-01-23	soc/amd/picasso/pcie_gpp: Remove duplication in pirq_data declaration	Raul E Rangel
	There is no reason to duplicate the table. BUG=b:170595019 BRANCH=zork TEST=boot zork with pci=nomsi and verify /proc/interrupts didn't change Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ief714266cdb1b4f89afd0d9e50238200b87687ef Reviewed-on: https://review.coreboot.org/c/coreboot/+/49367 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-01-23	soc/amd/picasso/pci_gpp: Replace the swizzle string with a u8 array	Raul E Rangel
	I think it makes the code a bit cleaner. BUG=b:170595019 BRANCH=zork TEST=boot zork with pci=nomsi and verify /proc/interrupts didn't change Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ib5e8e5b690d9612e8ae257f5d15c25122e1c91e6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49842 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-01-23	soc/amd/picasso/pcie_gpp: Add clarifying comment	Raul E Rangel
	Each bridge can only have one device. BUG=b:170595019 BRANCH=zork TEST=none Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I7e476221dfcabc841cc1ed4bc4b1175c0652dcfe Reviewed-on: https://review.coreboot.org/c/coreboot/+/49841 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-01-08	soc/amd/picasso: Generate GNB IO-APIC PCI routing table	Raul E Rangel
	This adds support for generating a PCI routing table that routes to the GNB IO-APIC. This means we no longer need to route to the FCH IO-APIC for PCI interrupts. BUG=b:170595019 TEST=Boot ezkinil to OS with `pci=nomsi amd_iommu=off` and verify all peripherals are working CPU0 CPU1 0: 112 0 IO-APIC 2-edge timer 1: 0 99 IO-APIC 1-edge i8042 4: 0 2523 IO-APIC 4-edge ttyS0 5: 34632 0 IO-APIC 5-fasteoi mmc1 7: 5646 0 IO-APIC 7-fasteoi pinctrl_amd 8: 0 0 IO-APIC 8-edge rtc0 9: 0 33 IO-APIC 9-fasteoi acpi 10: 88258 0 IO-APIC 10-edge AMD0010:00 11: 0 32485 IO-APIC 11-edge AMD0010:01 24: 3301 0 amd_gpio 3 cr50_i2c 25: 0 235214 IO-APIC 28-fasteoi amdgpu 26: 67408 0 IO-APIC 31-fasteoi xhci-hcd:usb1 27: 0 488876 IO-APIC 8-fasteoi mmc0 28: 1265 0 amd_gpio 9 PNP0C50:00 29: 656 0 amd_gpio 12 ELAN9004:00 30: 413 0 amd_gpio 31 chromeos-ec 31: 14153 0 IO-APIC 4-fasteoi ath10k_pci 32: 2 0 sysfstrig0 cros-ec-accel_consumer3 33: 2 0 sysfstrig0 cros-ec-accel_consumer0 34: 6 0 amd_gpio 62 rt5682 35: 0 38937 IO-APIC 29-fasteoi snd_hda_intel:card0, ACP3x_I2S_IRQ Cq-Depend: chrome-internal:3452710 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I3211ab351a332fafb7b5f9ef486bb6646d9a214c Reviewed-on: https://review.coreboot.org/c/coreboot/+/48668 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-01-06	soc/amd/picasso: Correctly populate the PCI interrupt line register	Raul E Rangel
	The PCI interrupt line registers are used as a last resort if routing can't be fetched from either ACPI or the MPTable. This change correctly sets the registers. It overrides the pirq_data set by the mainboards since the routing is fixed in AGESA. BUG=b:170595019 TEST=Boot ezkinil with `pci=nomsi,noacpi amd_iommu=off noapic` Verified all PCI peripherals are still functional. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: If5d4d8f613c8d0fa9b43cefa804824681c3410d6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48665 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-06	soc/amd/picasso: Fix ACPI PCI routing table	Raul E Rangel
	The original routing table did not handle all 8 INTx interrupts. Additionally it also didn't take the swizzling into account. Now that we know how AGESA programs the routing table we can correctly generate it. We still route the PCI interrupts through the FCH IOAPIC. A follow up will have the GNB IOAPIC handle the PCI interrupts. There is still work to be done to fix the legacy PCI_IRQ register for each PCI device. We can then remove the mainboard_pirq_data from each mainboard. BUG=b:170595019 TEST=Used ezkinil Boot kernel with `pci=nomsi amd_iommu=off noapic` and `pci=nomsi amd_iommu=off` then verified system was usable and verified /proc/interrupts looked correct. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I2b2cce9913081d5cd456043ba619a79c1dfd4a8e Reviewed-on: https://review.coreboot.org/c/coreboot/+/48632 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-11-18	include/device/pci_ids: add model number to PCIe port and bus devices	Felix Held
	Different models within family 17h have different PCI IDs for their PCIe GPP port and internal bus devices. Change-Id: I386df908ce5451b4484be2a2e4a9018c3d47d030 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47677 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-07-30	soc/amd/picasso: Split ops for internal and external PCIe GPP bridges	Furquan Shaikh
	This change splits the device operations for internal and external PCIe GPP bridges so that the external bridges use `pciexp_scan_bridge()` instead of `pci_scan_bridge()`. `pciexp_scan_bridge()` is required for external GPP bridges to enable ASPM on downstream devices if supported. BUG=b:162352484 TEST=Verified on Trembyle: $ lspci -s 1:00.0 -vvv \| grep ASPM LnkCap: Port #0, Speed 2.5GT/s, Width x1, ASPM L0s L1, Exit Latency L0s <4us, L1 <64u ClockPM+ Surprise- LLActRep- BwNot- ASPMOptComp+ LnkCtl: ASPM L1 Enabled; RCB 64 bytes Disabled- CommClk L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ L1_PM_Substates+ L1SubCtl1: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: Ice2aa3e4758adccf7b0b89d4222fc65a40761153 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44016 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Peers <epeers@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-10	soc/amd/picasso: Add driver for handling PCIE GPP bridges	Furquan Shaikh
	This change adds a driver pcie_gpp.c which provides device_operations for external and internal PCIe GPP bridges. These device operations include standard PCI bridge operations as well as operations for generating ACPI node for the device and returning appropriate ACPI name for it. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I9f8809c2735bdc09435deda91a570c89e71e8062 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43312 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>