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2023-01-12soc/amd/mendocino: Use common fsp-s preloaderFred Reitberger
Use the common preloader for fsp-s Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I74ef10347c37c8371156f89da9f234d170ab1aa6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71846 Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-01-12soc/amd/mendocino/include/soc/southbridge.h: Use BIT macro for consistencyFred Reitberger
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I2dd17774b79c5adb64c2575ac55dec476c434842 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71843 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-01-12soc/amd/mendocino: Remove TODO after reviewFred Reitberger
Remove TODO comment after reviewing against mendocino ppr #57243, rev 3.00 BUG=b:263563246 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Id517ce6e5f5bee5deffe509d748b16be0eefca96 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71842 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2023-01-12soc/amd/mendocino/include/platform_descriptors: remove TODO after reviewFelix Held
This header file is correct for Mendocino, so remove the TODO. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I85b47491863bff731b86cf0523253cb547dbb76a Reviewed-on: https://review.coreboot.org/c/coreboot/+/71794 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-09treewide: Remove unused <cpu/amd/msr.h>Elyes Haouas
Change-Id: Id24a7c7db24f49672df9d5ceefec5b7596f23e09 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64939 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-01-09soc/amd: Remove dummy SOC_SPECIFIC_OPTIONSElyes Haouas
Change-Id: I080b7b579338c3cf342beabda54f43f525d8b65c Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71679 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-01-09soc/amd/mendocino/Kconfig: Remove TODO after reviewFred Reitberger
Remove TODO comments after reviewing against mendocino ppr #57243, rev 3.00 BUG=263563246 TEST=build skyrim Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Ie56d481dd8b6b4e0a1e3d50f4ce75f50231fe4dc Reviewed-on: https://review.coreboot.org/c/coreboot/+/71719 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-04soc/amd/mendocino: Hook up UPD dxio_tx_vboost_enable for PCIe optimizationChris.Wang
Add the UPD dxio_tx_vboost_enable for PCIe optimization. It will impact the PCIe signal integrity, need to double-confirm the SI result after enabling this setting. BUG=b:259622787 BRANCH=none TEST=confirm the setting has been set correspondingly with checking the FSP log. Signed-off-by: Chris.Wang <chris.wang@amd.corp-partner.google.com> Change-Id: I05ae5b3091219e0cb1fe469c929fad6a725db678 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71562 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-03soc/amd/mendocino/psp_verstage/Makefile.inc: Remove path to non-existent ↵Elyes Haouas
directory Found using 'Wmissing-include-dirs' command option. Fix: cc1: error: ../../src/soc/amd/mendocino/psp_verstage/include: No such file or directory [-Werror=missing-include-dirs] Change-Id: I1cc084abc7a9bfed760350f304dd074081a7eebf Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71586 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-12-27tree/acpi: Replace constant "Zero" with actual numberFelix Singer
Change-Id: I5a3e3506415f424bf0fdd48fc449520a76622af5 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71525 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-24soc/amd/mendocino: Split the EFS from the AMDFW bodyKarthikeyan Ramasubramanian
Contents of unsigned AMDFW in RW sections are verified twice in PSP verstage - first time by vboot verifying the firmware body, second time by CBFS verification while the file is loaded to update PSP about the boot region. This redundant verification adds to boot time. Minimize the redundancy by splitting the EFS header from the AMDFW body and keep them as 2 separate CBFS files. This helps to improve the boot time by another 25 ms. BUG=None TEST=Build Skyrim BIOS image and boot to OS. Observe boot time improvement of ~25ms. Before: 6:end of verified boot 363,676 (16) 11:start of bootblock 641,392 (277,716) After: 6:end of verified boot 361,655 (16) 11:start of bootblock 616,967 (255,312) Change-Id: Ib18a4f5c6781e5a7868e9395c0f1212da0823100 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70839 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-21vc/amd,soc/amd/mendocino: Add SVC_CMD_GET_PREV_BOOT_STATUSKarthikeyan Ramasubramanian
Add an SVC command to get the previous boot status. If there is any pre-x86 boot failure in the previous boot cycle, PSP stores it in warm reset persistent register and triggers a warm reset. PSP verstage on the subsequent boot gets the previous boot status and reports any failure to the vboot before a FW slot is selected. BUG=b:242825052 TEST=Build Skyrim BIOS image and boot to OS in Skyrim. Trigger a failure scenario by corrupting certain firmware blobs and observe that PSP reports the failure boot status. On a normal boot, observed that PSP reports successful boot. Change-Id: I440deee560b72c80491bfdd7fda38a1c3a4299e5 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70381 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-20soc/amd/mendocino: add dptc tablet mode supportChris.Wang
add dptc support for different power parameter on tablet/clamshell mode. BUG=b:257187831 BRANCH=none TEST=validate the parameter change for each mode by AGT. Signed-off-by: Chris.Wang <chris.wang@amd.corp-partner.google.com> Change-Id: I96e04d113d18b42f3457056a5e4fa311ceccffb3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70670 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
2022-12-14soc/amd/*/config: drop invalid commentFelix Held
Since commit 28e61f16341f ("device: Use __pci_0_00_0_config in config_of_soc()") config_of_soc() was changed form being an actual function to a macro for the __pci_0_00_0_config struct pointer generated by util/sconfig. This change didn't only improve linker optimizations, but also turned runtime errors into link-time errors, so it's guaranteed that __pci_0_00_0_config won't be NULL and config_of_soc() won't "return" NULL. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id99ceaa9f7a70788da3f3068fb3da92d34fb6361 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70732 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-12-09soc/amd/mendocino: Enable LPC SPI DMAKarthikeyan Ramasubramanian
Enable LPC SPI DMA. This helps with ~20ms boot time improvement while loading various components synchronously. BUG=None TEST=Build Skyrim BIOS image and boot to OS. Observe a boot time improvement of ~20 ms. Before: Total Time: 1,503,032 After: Total Time: 1,485,536 Change-Id: I4dd57d46ae9bd664d57178d34b5beda872ed2cdb Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70383 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-08vc/amd/fsp/mendocino/FspmUpd: don't use pointers for usb_phy configFelix Held
The size of a pointer changes between a 32 and 64 bit coreboot build. In order to be able to use a 32 bit FSP in a 64 bit coreboot build, change the pointer in the UPDs to a uint32_t to always have a 32 bit field in the UPD for this. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I419fef73d2881e323487bc7fe641b2ac4041cb17 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70135 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-12-06sb,soc/amd: Remove unused southbridge_io_trap_handler()Kyösti Mälkki
At the moment IO trap is not implemented for AMD platforms. Change-Id: Ib62ac4e4e418a8bab80c30dfb5183ecd8beb998d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70360 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-30soc/amd/mendocino: Enhance DPTC_INPUT to support 13 DPTC thermal parametersEricKY Cheng
Expand DPTC_INPUT macro to supoort 13 DPTC thermal table parameters for dynamic table switching support. BRANCH=none BUG=b:232946420 TEST=emerge-skyrim coreboot Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com> Change-Id: I6d6a00f0eca0b0941860b9bc75da41d7a10d60e8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68649 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-11-25ACPI: Use common code for MADT LAPIC NMIsKyösti Mälkki
Use the broadcast ID to deliver LINT1 as NMI to all CPUs, instead of listing individual LAPIC IDs. Change-Id: Iaf714d8c2aabd16c59c3bcebc4a207406fc85ca9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69527 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-24soc/amd: Define post codesMartin Roth
For the most part, this doesn't change any post codes, simply making the existing post-codes into macros. picasso/romstage.c did get a couple of post codes removed to match the other files. The POST_ROMSTAGE and POST_BOOTBLOCK codes are intended to become global at some point, while the POST_AGESA and POST_PSP codes would stay AMD specific. Change-Id: I007a09b6a3ed3280bac674cd74e298ec5c408ab7 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69867 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-23soc/amd/*/fsp_m_params: rework local USB PHY table updateFelix Held
Update the fields that need to be updated directly in the local static usb_phy_config struct instead of dereferencing the pointer written to the corresponding UPD field. This will allow updating the type of UPD field in a follow-up commit to enable 64 bit coreboot builds. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I44a9fe719e6803fc957fee3db13b261489ed313d Reviewed-on: https://review.coreboot.org/c/coreboot/+/69896 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-11-23soc/amd/*/Makefile: fix readelf parameters to get bootblock sizeFelix Held
This ports forward part of commit df0968062622 ("soc/amd/picasso: Add support for 64bit builds") to the newer AMD SoCs. Use -Wl instead of -l to get the output format that the commands in the Makefile expect to extract the value for PSP_BIOSBIN_SIZE. Without this change, readelf will split the output into two lines in case of a 64 bit coreboot build. This results in invalid amdcompress and amdfwtool command lines which will cause the amdfwtool call to fail with Error: BIOS binary destination and uncompressed size are required With the old readelf -l command we get this output in a 64 bit build: Program Headers: Type Offset VirtAddr PhysAddr FileSiz MemSiz Flags Align LOAD 0x0000000000000080 0x0000000002030000 0x0000000002030000 0x0000000000010000 0x0000000000010000 RWE 0x10 while we get the correct output in a 32 bit build: Program Headers: Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align LOAD 0x000060 0x02030000 0x02030000 0x10000 0x10000 RWE 0x20 With readelf -Wl we also get the expected output in a 64 bit build: Program Headers: Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align LOAD 0x000080 0x0000000002030000 0x0000000002030000 0x010000 0x010000 RWE 0x10 TEST=This fixes the 64 bit build on Cezanne with some follow-up patches applied. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I35f9feda4d0da3546592dfac233ca66732bd5464 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69895 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-11-21soc/amd/mendocino: Increase CBFS_MCACHE sizeKarthikeyan Ramasubramanian
CBFS_MCACHE is currently experiencing overflow with CBFS verification enabled. Reduce the pre-x86 cbmem console size from ~5.5 KiB to 4 KiB. This reduction along with the available free space in PSP shared buffer (32 KiB) helps to increase the CBFS_MCACHE size from 8 KiB to required 14 KiB. BUG=b:259342909 TEST=Build and boot to OS in Skyrim. Ensure that there are no CBFS mcache overflows. FMAP: area COREBOOT found @ 80a000 (8347648 bytes) VB2:vb2_digest_init() 0 bytes, hash algo 2, HW acceleration unsupported CBFS: mcache @0x00019a40 built for 67 files, used 0x19a0 of 0x1c00 bytes CBFS: Found 'apu/amdfw_a' @0x0 size 0x3ff80 in mcache @0x0001b640 VB2:vb2_digest_init() 262016 bytes, hash algo 2, HW acceleration enabled Ensure that firmware_CbfsMcache FAFT test is successful. Change-Id: I35e1a8c6d73e0870b6a43aac604f83a0b6c3aabe Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69827 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-17soc/amd: Use ioapic helper functionsKyösti Mälkki
Calling setup_ioapic() was only correct for the IOAPIC routing GSI 0..15 that mimic legacy PIC IRQs. Change-Id: Ifdacc61b72f461ec6bea334fa06651c09a9695d6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55571 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-14soc/amd/*/root_complex: use FSP HOB iterator functionsFelix Held
Use the newly added functions to iterate over the FSP HOBs to report the resources used by FSP to the resource allocator instead of open coding the iteration over the HOBs in the SoC code. TEST=Patch doesn't change reported resources on Mandolin Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I67ca346345c1fa08b008caa885d0a00d2d5afb12 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69476 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-14arch/x86/Kconfig: Move AMD stages arch to common codeArthur Heymans
Use VBOOT_STARTS_BEFORE_BOOTBLOCK to determine whether the VERSTAGE needs to be build as x86 stage. Change-Id: I126801a1f6f523435935bb300f3e2807db347f63 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69505 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-11-11soc/amd/root_complex: don't skip reporting IOAPIC resource in !hob caseFelix Held
When no HOB list is found, not only adding the resources reported by the FSP were skipped, but also adding the GNB IOAPIC resource was skipped. Fix this bug by moving the reporting of the GNB IOAPIC resource before the resources reported in the FSP HOBs to not skip the IOAPIC resource when there's no HOB list. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I9174c8d7e5e94144187d27210e12f2dca3a6010f Reviewed-on: https://review.coreboot.org/c/coreboot/+/69460 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-10/: Remove "ERROR: "/"WARNING: " prefixes from log messagesElyes Haouas
It is no longer necessary to explicitly add "ERROR: "/"WARNING: " in front of every BIOS_ERR/BIOS_WARN message. Change-Id: I22ee6ae15c3d3a848853c5460b3b3c1795adf2f5 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69405 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-07soc/amd/mendocino: Enable x86 SHA acceleratorKarthikeyan Ramasubramanian
Enable x86 SHA accelerator for use by VBOOT library. This is useful when CBFS verification verifies the hash of the file being loaded in x86. BUG=b:227809919 TEST=Build and boot to OS in Skyrim. Observe a boot time improvement of ~10 ms with CBFS verification enabled. Change-Id: I14efe7be66f28f348330580d2e5733e11603a023 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68954 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-04src/soc/amd/mendocino: Enable override of MAINBOARD_BLOBS_DIRNikolai Vyssotski
When using site-local we need to have ability to override MAINBOARD_BLOBS_DIR with a different location (presumably somewhere in site-local). site-local Makefiles.inc should be pulled in first (different CL) allowing MAINBOARD_BLOBS_DIR to be overwritten. Change-Id: I028042b947887d1182642ad4482dd1bba7ad8e23 Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68801 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-11-04soc/amd/*/data_fabric: Use common device opsFred Reitberger
Use the common device ops instead of an soc-specific device ops. TEST=builds for each soc Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I1804200c3c3f5ab492d237f4b03484c383862caf Reviewed-on: https://review.coreboot.org/c/coreboot/+/69174 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-04soc/amd/mendocino/data_fabric.c: Make function more genericFred Reitberger
Make the data_fabric_acpi_name function more generic, in preparation to move it to common. TEST=build chausie, dump ACPI tables, and inspect DFD0 to DFD7 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I77140d8d0d6bf3e048b737de03d18142a6e23c1d Reviewed-on: https://review.coreboot.org/c/coreboot/+/69172 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-04soc/amd/*/data_fabric: Move register offsets to socFred Reitberger
Morgana/Glinda have a different register mapping for data fabric access, although the registers themselves are mostly compatible. The register layouts defined by each soc capture the differences and the common code can use those. Move the register offsets to soc headers and update the offsets for morgana/glinda per morgana ppr #57396, rev 1.52 and glinda ppr #57254, rev 1.51 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I9e5e7c85f99a9afa873764ade9734831fb5cfe69 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69074 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-04soc/amd: Specify memory types supported by each chipMartin Roth
This change disables support for memory types not used by each of the chips. This will in turn remove the files for those memory types from the platform builds. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I8c7f47b43d8d4a89630fbd645a725e61d74bc2a5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68994 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-03soc/amd/mendocino/data_fabric: Add register bitslice structFred Reitberger
Add structs to define the data_fabric register bitfields. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I01dcea783542ecc0a761191907c1273016f854c2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69070 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-03soc/amd/*/data_fabric: move data_fabric_set_mmio_np to commonFred Reitberger
The data_fabric_set_mmio_np function is effectively identical, so move it to common code. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I58e524a34a20e1c6f088feaf39d592b8d5efab58 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69067 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-03soc/amd: Include <cpu/cpu.h> instead of <arch/cpu.h>Elyes Haouas
Also sort includes. Change-Id: Iea29938623fe1b2bcdd7f869b0accbc1f8758e7a Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69033 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-29soc/amd/*/acpi/mmio.asl,sb_fch.asl: hide AAHB deviceFelix Held
Don't set bit 2 in _STA in order for Windows not to show a warning about an unknown device in the device manager for this device. Since the _STA object just returns a constant, a name definition can be used instead of a method definition. TEST=The unknown device with device instance path ACPI\AAHB0000\0 disappeared from the device manager in Windows 10 build 19045 on a Mandolin board with a Picasso APU. Just shutting down and then booting it again won't clear some internal state in Windows, so a reboot is needed instead for the change to become visible. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8cb1712756c3623cc3ea16210af69cde0fa18f62 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68961 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-10-28soc/amd/mendocino: Add code for printing STB to boot logMartin Roth
This adds the mendocino specific code for printing the STB data to the boot log. It still needs to be enabled in the mainboard to be used. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I249507a97ed6c44805e9e66a6ea23f200d62cf66 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68544 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-28soc/amd/mendocino: Expand extra 5 DPTC thermal related profilesEricKY Cheng
Expand extra 5 DPTC thermal related profiles for Dynamic Thermal Table Switching support. BRANCH=none BUG=b:232946420 TEST=emerge-skyrim coreboot Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com> Change-Id: Ie03de155325cbb340fce09848327ff7fa33ab1fd Reviewed-on: https://review.coreboot.org/c/coreboot/+/68469 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com>
2022-10-26soc/amd/mendocino: Enable GPP clk req disabling for disabled devicesRobert Zieba
Enable GPP clk req disabling for disabled PCIe devices. If a clk req line is enabled for a PCIe device that is not actually present and enabled then the L1SS could get confused and cause issues with suspending the SoC. BUG=b:250009974 TEST=Ran on skyrim proto device, verified that clk reqs are set appropriately Change-Id: I6c840f2fa3f9358f58c0386134d23511ff880248 Signed-off-by: Robert Zieba <robertzieba@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68139 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-26soc/amd/mendocino: Add GSVCD rangeKarthikeyan Ramasubramanian
Add region/range of SPI ROM to be verified by Google Security Chip (GSC). BUG=b:227809919 TEST=Build and boot to OS in Skyrim with CBFS verification enabled. Change-Id: If8a766d9a7ef26f94e3ab002a9384ba9d444dd1f Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66945 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-10-26soc/amd/mendocino: Update build rules for PSP BIOS imageKarthikeyan Ramasubramanian
Do not compress PSP BIOS image when CBFS verification is enabled. Otherwise when a file is added to CBFS, cbfstool is not able to find the metadata hash anchor magic in the compressed PSP BIOS image. BUG=b:227809919 TEST=Build and boot to OS in Skyrim with CBFS verification enabled for both x86 and PSP verstage. Change-Id: Iaed888b81d14ede77132ff48abcfbeb138c01ce4 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68136 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-10-26soc/amd/mendocino: Reserve more space for metadataKarthikeyan Ramasubramanian
With CBFS verification enabled, CBFS file header + file name + metadata consumes more than 64 bytes. Hence reserve additional space aligned to the next 64 bytes. BUG=b:227809919 TEST=Build and boot to OS in Skyrim with CBFS verification enabled. Change-Id: I2b7346e2150835443425179048415f3b27d89d89 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66944 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-26soc/amd: Add amdfw.rom in coreboot.preKarthikeyan Ramasubramanian
This change ensures that amdfw.rom binary containing metadata hash anchor is added before any file is added to CBFS. This will allow to verify all the CBFS files that are not excluded from verification. BUG=b:227809919 TEST=Build and boot to OS in Skyrim with CBFS verification enabled using x86 and PSP verstages. Change-Id: Id4d1a2d8b145cbbbf2da27aa73b296c9c8a65209 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66943 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-10-23soc/amd/mendocino: Add STB Spill-to-DRAM enumMartin Roth
This is the enum value to initialize the Smart Trace Buffer's Spill-to-DRAM feature. More information on how this is used is available in the STB Linux kernel driver. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Iab2e5fb121902959ddd0e7c8cca930a327b69291 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68686 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2022-10-22soc/amd/*/i2c.h: Make definition more accurateFred Reitberger
Make GPIO_I2C_MASK macro more accurate by using the GPIO_I2Cx_SCL definitions instead of BIT(x). Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I13fc376552068a64768fe1cf9f1c09cca1768aed Reviewed-on: https://review.coreboot.org/c/coreboot/+/68682 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-21soc/amd/*/smi.h: Use BIT() for clarityFred Reitberger
Use the BIT() macro for single-bit constants. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I490f0093d55813260fcdb7303a94accfa90e75e4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68548 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-10-21soc/amd/*/uart: cleanup includesFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I59ab9c2eaa65d974d418123e87e9afe65b1168cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/68633 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-20soc/amd/*/uart: commonize UART code and MMIO device driverFelix Held
Now that the SoC-specific UART controller data and the common code part are cleanly separated, move the code to the common AMD UART support block folder. The code is identical to the UART code in Cezanne, Mendocino, Morgana and Picasso while Stoneyridge doesn't use the parts related to the MMIO device driver. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id9429dac44bc02147a839db89d06e8eded7f1af2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68561 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-20soc/amd: move set_uart_config prototype to common UART headerFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I97860292fd3cd0330fec40edb31089cd6608906b Reviewed-on: https://review.coreboot.org/c/coreboot/+/68560 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-20soc/amd: move all AOAC function prototypes to amdblocks/aoac.hFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3deae150cd1e20fff6507a0f0ba6a375fca430e5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68559 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-20soc/amd/mendocino/uart: introduce and use soc_get_uart_ctrlr_infoFelix Held
Introduce and use soc_get_uart_ctrlr_info to access the uart_info array to further decouple uart_info from the code as preparation to factor out most of the code to a common implementation. In order to slightly reduce the number of function calls, pass the size of and pointer to uart_info to get_uart_idx as a parameter instead of calling again soc_get_uart_ctrlr_info in get_uart_idx despite all callers already having the information form the soc_get_uart_ctrlr_info call. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8cfea274f4c9e908c11429199479aec037a00097 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68536 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-20soc/amd/*/uart: add missing soc/iomap.h includeFelix Held
soc/iomap.h provides the UART base address information used in the uart_info struct. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I7defd135dc888cfc7d6e1c106d72116425560576 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68532 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-20soc/amd: introduce and use common soc_uart_ctrlr_info structFelix Held
The SoC's uart_info structs all use the same anonymous uart_info struct definition, so create a named struct for this in the common AMD SoC UART header and use it in the SoC code. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id183a3c838c6ad26e264c2a29f3c20b00f10d9be Reviewed-on: https://review.coreboot.org/c/coreboot/+/68530 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-20soc/amd/mendocino/uart: separate data and codeFelix Held
The goal of this is to be able to move most of the code over to the common AMD blocks. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5077681b64dd68351340bd179838a174d8df1701 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68528 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-18soc/amd: factor out writing extended PM registers in FADTFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I59985f283f1694beeacb0999340111146fa3f39b Reviewed-on: https://review.coreboot.org/c/coreboot/+/68494 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-18soc/amd/*/i2c: Move reset_i2c_peripherals to i2c.cFred Reitberger
Move i2c SoC related code from early_fch.c to i2c.c TEST=build boards for each SoC Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I69d4b32cf95ce74586bd8971c7ee4b56c1c2fc04 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68499 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2022-10-17soc/amd: factor out common noncar bootblockFelix Held
This code is identical for all non-CAR AMD SoCs, so factor it out to soc/amd/common/block/cpu/noncar/bootblock.c to avoid code duplication. Also integrate the bootblock.c improvement to include cpu/cpu.h which provides cpuid_eax from commit 68eb439d8091 ("soc/amd/picasso: Clean up includes"). Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I42e4aa85efd6312a3ab37f0323a35f6dd7acd8e6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68431 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-17soc/amd/*/smihandler: Make fch_apmc_smi_handler commonFred Reitberger
Rename soc/amd/common/block/cpu/smm/smi_ampc_helper.c to smi_apmc.c and add the fch_apmc_smi_handler function. Remove the duplicated function from picasso, cezanne, mendocino, and morgana SoC. The stoneyridge soc does not implement the APM_CNT_SMMINFO handler, so give the handler a unique name that does not conflict with the common handler name. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I2e6fb59a1ee15b075ee3bbb5f95debe884b66789 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68441 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-10-15treewide: Use 'fadt->x_pm1a_evt_blk.addrl = fadt->pm1a_evt_blk'Felix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id3002dc976b82f71b1f60a6e32b16d60a7bbbead Reviewed-on: https://review.coreboot.org/c/coreboot/+/68427 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-10-14soc/amd/*: Hook up IOMMU ops in devicetreeArthur Heymans
This removed the need to maintain a PCI driver. Change-Id: I43def81d615749008fcc9de8734fa2aca752aa9d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68146 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-10-14soc/amd/*: Hook up LPC ops in devicetreeArthur Heymans
This removes the need for a PCI driver. Change-Id: I6674d13f434cfa27fa6514623ba305af6681f70d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68144 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-10-14soc/amd/*: Hook up SMBus ops to devicetreeArthur Heymans
This removes the need for a PCI driver. Change-Id: Iab75f8c28a247f1370f4425e19cc215678bfa3e5 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68140 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-10-14soc/amd: factor out common eMMC codeFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If5447f9272183f83bc422520ada93d3cfd96551e Reviewed-on: https://review.coreboot.org/c/coreboot/+/68415 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-10-13soc/amd/*: Hook up GPU ops in devicetreeArthur Heymans
This removes the need for a PCI driver. Change-Id: I4b499013a80f5c1bd6ac265a5ae8e635598d9e6c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68148 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-13soc/amd/*: Hook up GPP bridges ops to devicetreeArthur Heymans
This removes the need for a PCI driver. Change-Id: I8e235d25622d0bd3f1bb3f18ec0400a02f674a6d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68147 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-13soc/amd/acp: Hook up ops in devicetreeArthur Heymans
This removes the need for a PCI driver. Change-Id: Id25016703d1716930d9b6c6d1dab5481b10aca17 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68145 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-13soc/amd/mendocino: Use devicetree ops over pci driverArthur Heymans
Mendocino is a SoC so it makes sense to statically use ops instead of matching them to PCI DID/VID at runtime. Change-Id: I5619c8ad42cdeb019cb7294da884909df64a2211 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68141 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-13soc/amd/*: Hook up device_operations in chipset.cbArthur Heymans
This removes the need for a lot of boilerplate code in the soc code to hook up device_operations to devices. Change-Id: I2afc1855407910f1faa9bdd4e9416dd46474658e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67738 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-13soc/amd/*: Move emmc disabling to device opsArthur Heymans
This allows for reduced use of chip_operations in the followup patch and allows the allocator to skip over the used mmio. Change-Id: I4052438185e7861792733b96a1298201c73fc3ff Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68113 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-13payloads,src: Replace ALIGN(x, a) by ALIGN_UP(x, a) for clarityElyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I80f3d2c90c58daa62651f6fd635c043b1ce38b84 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68255 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-13soc/amd/*/psp_verstage/svc: Make svc.h macros commonFred Reitberger
The psp_verstage/svc.h SVC_CALLx macros are virtually identical between picasso/cezanne/mendocino, so move to common. TEST=timeless builds are identical Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I86a8d9b043f68c01ee487f2cdbf7f61934b4a520 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68277 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-12treewide: Use 'fadt->x_pm1a_cnt_blk.addrl = fadt->pm1a_cnt_blk'Elyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Ic48c5c165732c8397c06a2362191a94ae5805cf1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68276 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-12treewide: Use 'fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk'Elyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I7ddb4ea792b9a2153b7c77d2978d9e1c4544535d Reviewed-on: https://review.coreboot.org/c/coreboot/+/68275 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-12treewide: Use 'gpe0_blk' for 'x_gpe0_blk.addrl'Elyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I05d5097097b925a7bc8058f4c23e7c13a49f03c5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68273 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-12treewide: Use 'gpe0_blk_len' for 'x_gpe0_blk.bit_width'Elyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I581cacb6086d94fe65e6f4800454f447e1ada07b Reviewed-on: https://review.coreboot.org/c/coreboot/+/68272 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-12treewide: Use 'fadt->pm_tmr_len' for 'x_pm_tmr_blk.bit_width'Elyes Haouas
Change-Id: Id4e2939b74ec93f50a4bedd0069090f0775b0556 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68271 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-12treewide: Use 'fadt->pm1_cnt_len' for 'x_pm1a_cnt_blk.bit_width'Elyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I4e468e6bb58adc44bd66149eb79dc885dbf73c67 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68270 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-12treewide: Use 'fadt->pm1_evt_len' for 'x_pm1a_evt_blk.bit_width'Elyes Haouas
Change-Id: I1e51ccad32f1c5e692c76b331eedf4d3bb260d38 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68269 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-08soc/amd/mendocino/psp_verstage: Remove TODO commentKarthikeyan Ramasubramanian
PSP verstage has been successfully enabled and this makefile looks good. Hence removing a TODO comment. BUG=b:239090306 TEST=Build Skyrim BIOS image. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: Ic3cd55171fd1e4d74fac72f0b0b92dc80e533b5c Reviewed-on: https://review.coreboot.org/c/coreboot/+/68227 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-07soc/amd/{CZN,MDN,PCO}: Fix building with only single RW regionMatt DeVillier
apu/amdfw_a was only getting added to CBFS when VBOOT_SLOTS_RW_AB was selected, but needs to be added in the RW_A only case as well (VBOOT_SLOTS_RW_A). Since VBOOT_SLOTS_RW_AB selects VBOOT_SLOTS_RW_A, we can guard amdfw_a and _b separately and both will be added in the RW_AB case. TEST=build google/zork with VBOOT_SLOTS_RW_A or VBOOT_SLOTS_RW_AB selected, ensure amdfw_a and amdfw_b are added to correct CBFS regions as appropriate. Change-Id: Ic8048e869d7449eeb1ac10bfec4a5646b848d6a8 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68126 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-10-02soc/amd/(common,mendocino)/psp_verstage: Pass PSP FW hash tableKangheui Won
Copy AMD PSP fw hash table into memory, then pass it to the PSP. The PSP will use this hash to verify it's the correct firmware bundled with coreboot build and not replaced. BUG=b:203597980 TEST=Build Skyrim BIOS image with the hash table and boot to OS after PSP verified the binaries against the hash table. Change-Id: I84bea97c89620d0388b27891a898ffde77052239 Signed-off-by: Kangheui Won <khwon@chromium.org> Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60291 Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Jon Murphy <jpmurphy@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-02soc/amd/mendocino: Add build rules to separate signed PSP/AMDFWKarthikeyan Ramasubramanian
Add build rules to separate signed PSP/AMDFW. Also add build rules to add the generated hash table containing SHA digest of individual PSP FW components into CBFS. This will allow verified boot to load and verify less components from SPI rom which means faster boot time. BUG=b:206909680 TEST=Build Skyrim with modified fmap and Kconfig Change-Id: If54504add72b30805b6874bee562e0b9482782b9 Signed-off-by: Kangheui Won <khwon@chromium.org> Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67260 Reviewed-by: Jon Murphy <jpmurphy@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-30soc/amd/cezanne,mendocino,picasso/uart: use write16p to avoid typecastsFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6e743068dfcf9d393096f775759181af1a1c470d Reviewed-on: https://review.coreboot.org/c/coreboot/+/67979 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-09-23soc/amd/mendocino: Add svc_set_fw_hash_tableKarthikeyan Ramasubramanian
Add new PSP svc call to pass psp firmware hash table to the PSP. psp_verstage will verify hash table and then pass them to the PSP. The PSP will check if signed firmware contents match these hashes. This will prevent anyone replacing signed firmware in the RW region. BUG=b:203597980 TEST=Build and boot to OS in Skyrim. Change-Id: I512d359967eae925098973e90250111d6f59dd39 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67259 Reviewed-by: Robert Zieba <robertzieba@google.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-19amd/mendocino/root_complex: Throttle SOC during low/no batteryTim Van Patten
Use dynamic power and thermal configuration (DPTC) via ACPI ALIB calls to throttle the SOC when there is no battery or critically low battery, to enable the SOC to boot without overwhelming the AC charger and browning out. DPTC is not enabled for low/no battery mode with this CL. It will be enabled for Skyrim in a following CL. BRANCH=none BUG=b:217911928 TEST=Boot skyrim Signed-off-by: Tim Van Patten <timvp@google.com> Change-Id: Ifeddb99e97af93b40a5aad960d760e4c101cf086 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67189 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-19amd/mendocino/acpi/soc: Add DPTC SupportTim Van Patten
Add support for DPTC by calling SB.DPTC() as part of PNOT(). BRANCH=none BUG=b:217911928 TEST=Boot skyrim Signed-off-by: Tim Van Patten <timvp@google.com> Change-Id: Ifc332bfc4d273031c93b77673224b4f3c2871fb1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67694 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-19soc/amd/mendocino: Add low/no battery VRM limit registersTim Van Patten
Add DPTC Low/No battery VRM limit registers to throttle the SOC. BRANCH=none BUG=b:217911928 TEST=Build skyrim Signed-off-by: Tim Van Patten <timvp@google.com> Change-Id: I9c4ed227b54efbab9f03d6acf64b1160ad73f460 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67692 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-19amd/mendocino/root_complex: Set DPTC VRM limit valuesTim Van Patten
Set the DPTC VRM limit values for normal mode. BRANCH=none BUG=b:217911928 TEST=Boot skyrim Signed-off-by: Tim Van Patten <timvp@google.com> Change-Id: I2041a713323f039dcfdacdfa43e74cf450c3c0d1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67691 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-19soc/amd/mendocino: Add VRM limit DPTC registersTim Van Patten
Add VRM DPTC limit registers. These are required when throttling the SOC for low/no battery mode to prevent the SOC from overwhelming the charger. b/245942343 is tracking passing these additional fields to the FSP and having the FSP configure them. BRANCH=none BUG=b:217911928 TEST=Build skyrim Signed-off-by: Tim Van Patten <timvp@google.com> Change-Id: Ie62129d967192f9a9cf654b1854d7dbe4324802a Reviewed-on: https://review.coreboot.org/c/coreboot/+/67378 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-19soc/amd/mendocino/acpi: Add support for shared TPM_I2C controllerJan Dabros
There are platforms equipped with AMD SoC where I2C3 controller connected to TPM device is shared between X86 and PSP. In order to handle this, PSP acts as an I2C-arbitrator, where x86 (kernel) sends acquire and release requests to be accepted by PSP. Introduce new CONFIG for Mendocino SoCs similar to what we have for Cezanne. BUG=b:241878652 BRANCH=none Signed-off-by: Jan Dabros <jsd@semihalf.com> Change-Id: I015a24715271d2b26c0bd3c9425e20fb2987a954 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67674 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-09-15amd/mendocino: Control DPTC with only KconfigTim Van Patten
SOC_AMD_COMMON_BLOCK_ACPI_DPTC can be enabled conditionally for any skyrim boards, similar to mainboard/google/zork/Kconfig. This makes the value dptc_tablet_mode_enable redundant. This CL removes dptc_tablet_mode_enable so DPTC is controlled entirely with the Kconfig value SOC_AMD_COMMON_BLOCK_ACPI_DPTC. This means DPTC is only included for boards that actually enable it. BRANCH=none BUG=b:217911928 TEST=emerge-skyrim coreboot Signed-off-by: Tim Van Patten <timvp@google.com> Change-Id: I73fca5a16826313219247f452d37fb526ad4f4df Reviewed-on: https://review.coreboot.org/c/coreboot/+/67639 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-09-14acpi/soc: Conditionally include dptc.aslTim Van Patten
Conditionally include dptc.asl based on the Kconfig value SOC_AMD_COMMON_BLOCK_ACPI_DPTC. BRANCH=none BUG=b:217911928 TEST=Build zork TEST=Build guybrush TEST=Build skyrim TEST=Build majolica Change-Id: Idd94af8e8b2d7973abc0fb939e4600189e21656a Signed-off-by: Tim Van Patten <timvp@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67620 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-14cpu/amd/smm: Move MP & SMM init in a common placeArthur Heymans
Change-Id: I7c457ab69581f8c29f2d79c054ca3bc7e58a896e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64870 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-14soc/amd: Recalculate the field power in PSS table entryZheng Bao
Being divided by 1000 causes data loss and the loss is expand by muliplication. So we just set a lower divisor before muliplication. BUG=b:185922528 Change-Id: Ib43103cc62c18debea3fd2c23d9c30fb0ecd781b Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67050 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-09-14soc/amd/mendocino: Add support for separate RW A/B partition SPL fileFelix Held
Add support for having different Security Patch Level (SPL) table files in the read-only and the read-write A/B partitions. This allows the SPL table file in the main or RO FMAP partition to only cover the embedded firmware binaries in that partition and have a separate SPL file in the RW A and B partitions that covers the embedded firmware binaries in the RW partitions. BUG=b:243470283 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1ba8c370ce14f7ec88e7ef2f9d0b64d6bb4fa176 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67555 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-09-12soc/amd: Remove unsupported DPTC tablet mode settingsTim Van Patten
The following boards are setting DTPC tablet mode values without corresponding device tree values, meaning they are effectively setting "random" values for tablet mode: 1. Cezanne 2. Mendocino The device tree has tablet mode disabled, so the code should never be exercised, but this CL removes it entirely to cleanup "dead" code. BRANCH=none BUG=b:217911928 TEST=Build nipperkin TEST=Boot skyrim Signed-off-by: Tim Van Patten <timvp@google.com> Change-Id: Ide96f255b69670d1b4c37ca2f94cc3504a958b57 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67181 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-09-12soc/amd: Refactor DPTC Tablet ModeTim Van Patten
Refactor AMD DPTC tablet mode in preparation for adding low/no battery DPTC settings. 1. Refactor and simplify acpigen_write_alib_dptc() into the following functions: - acpigen_write_alib_dptc_default() - acpigen_write_alib_dptc_tablet() 2. Add device tree register value dptc_tablet_mode_enable to control whether DPTC tablet mode is enabled for a variant. 3. Add dptc.asl to perform the necessary ACPI checking before modifying the DPTC settings. BRANCH=none BUG=b:217911928 TEST=Build zork TEST=Build nipperkin TEST=Boot skyrim Change-Id: I2518fdd526868c9d5668a6018fd3570392e809c0 Signed-off-by: Tim Van Patten <timvp@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66994 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-09-07soc/amd/mendocino/Kconfig: Enable APOB_HASHFred Reitberger
Enable the APOB_HASH feature. This improves boot times by ~10ms. BUG=b:193557430 TEST=boot to OS and verify boot time improvement Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I9628b67cd3206ffdbef23162c453dc183c69e5a5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67377 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-16 11:38:17 +0000