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2021-07-14soc/amd: factor out check_mca to common codeFelix Held
Change-Id: I139d1fe41bad5213da8890c2867f275b6847e3e1 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56281 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-14soc/amd: move check_mca prototype to soc/amd/common/blocks/includeFelix Held
Change-Id: Ia489dbfba59c334cf29f96a4000cef73b9b797d4 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56279 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-14soc/amd/common/block/lpc: Don't disable the HOG bitRaul E Rangel
According to the AMD FCH architects, we should be using the default value for the NO_HOG bit. This fixes a problem where the SPI DMA no longer functions after the LPC init runs. BUG=b:179699789, b:192373221 TEST=Boot guybrush and see SPI DMA working Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: If015869657f36d3533f4ab9ebd1f54b0d4eb283a Reviewed-on: https://review.coreboot.org/c/coreboot/+/56233 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-07-14soc/amd/cezanne: Move APOB update into ramstageRaul E Rangel
There is no technical reason this needs to be done in romstage. Moving it into ramstage allow us (in future CLs) to use threads to pre-load the apob from SPI. BUG=b:179699789 TEST=Boot and Ezkinil and Guybrush and verify APOB update still work Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I960437ff4400645de5a3e7447fcdbc52de85943e Reviewed-on: https://review.coreboot.org/c/coreboot/+/56227 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-07-14soc/amd/common/block/apob: Fix incorrect printf formatRaul E Rangel
The %p format specifier already prints out 0x, so remove the 0x from the string. I also updated the other format specifiers to use the %# syntax to print out the 0x. BUG=b:179699789 TEST=see correct format. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I5b00d2c06687e549f69486eb5e18f7bed560b2ec Reviewed-on: https://review.coreboot.org/c/coreboot/+/56225 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-12soc/amd/{cezanne,common}: Enable IOMMU PCIe DeviceRaul E Rangel
This change only enables the IOMMU device. We still require the IVRS table to take advantage of the IOMMU. This will happen when the picasso IVRS code is moved into common. BUG=b:190515051 TEST=lspci shows IOMMU device 00:00.2 IOMMU: Advanced Micro Devices, Inc. [AMD] Device 1631 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I5c7cae3d25af5a45d48658ffa948a2856adc4346 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55737 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-07-02soc/amd/common/espi: Fix debug message log levelRaul E Rangel
BUG=none TEST=Boot with CONSOLE_LOGLEVEL_3 and no longer see the message printed. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I0bdb92f547ceb8be624521211f4a3b94a91dae22 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55972 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-07-02soc/amd/common/block/cpu: Cache the uCode to avoid multiple SPI readsRaul E Rangel
We are currently reading the uCode for each CPU. This is unnecessary since the uCode never changes. BUG=b:177909625 TEST=Boot guybrush and see "microcode: being updated to patch id" for each CPU. I no longer see CBFS access for each CPU. This drops device initialization time by 32 ms. Also boot Ezkinil and verify microcode was also updated. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I98b9d4ce8290a1f08063176809e903e671663208 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55987 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-07-02soc/amd/common/block/lpc: Add custom SPI DMA boot deviceRaul E Rangel
This is a copy of mmap_boot.c and mem_rdev_ro_ops. I split it up so it was easier to review. The next patches will add support for the SPI DMA controller. This will provide a minor speed up vs using mmap reads. It will also provide the facilities to perform asynchronous SPI loading. BUG=b:179699789 TEST=Boot guybrush to OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Id26e2a69601d0f31e256d0010008904a447c8e21 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55854 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-06-30soc/amd/common/fsp/dmi.c: Fix Type 17 DMI reportingNikolai Vyssotski
With two versions of *speed_mhz_to_reported_mts() we need to call the correct one based on the reported memory type. BUG=b:184124605 TEST="dmidecode --type 17" in OS on Guybrush Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Change-Id: I92e834097546e3ef7130830444a80f818bdea3d5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55852 Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-28soc/amd/cezanne: Add call to mb to configure eSPI requirementsMartin Roth
When initializing espi early, there may be mainboard requirements to configure the bus properly. This allows the mainboard to do that. BUG=192100564 TEST=Build along with next patch, eSPI works on guybrush Change-Id: Icc02877a09b8f8ed20fd1b04f3cee0509f1a85c5 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55863 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-06-23soc/amd/common/acp: Populate _WOV ACPI methodKarthikeyan Ramasubramanian
In order to support Audio Co-processor (ACP) DMIC hardware runtime detection on the platform, ACPI _WOV method is populated on the concerned ACP device. This method returns the ACPI Integer value as 1 if ACP DMIC exists on the platform. BUG=b:182960979 TEST=Build and boot to OS in guybrush. Ensure that the _WOV ACPI method is populated under the scope of ACP device. Scope (\_SB.PCI0.GP41.ACPD) { Method (_WOV, 0, NotSerialized) { Return (One) } } Change-Id: Ide84f45f5ea2ae42d5efe71ac6d1595886157045 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55029 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-23soc/amd/common/block/cpu/noncar/memmap: move BERT region back into CBMEMFelix Held
The original reason the BERT table was moved out of CBMEM was because the OS was not able to access the region. This happened because the CBMEM region was marked as type 16 in the e820 table. The OS isn't aware of this type, so it prevents any drivers from accessing it. Depthcharge now correctly labels the CBMEM region as reserved in the e820 table so we can move the BERT table into CBMEM. TEST=BERT ACPI table generation still works on AMD/Mandolin with SeaBIOS as payload and BERT region inside CBMEM is inside a BIOS-e820 reserved range. BERT generation also works on Zork with depthcharge. Link: https://crrev.com/c/2939677 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie640e91c19ae5f9b275cc333284b4be34211fbf6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55279 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-06-22soc/amd/common: Add GPIO config for native func w/ output driveMartin Roth
Our existing native function gpio configuration macro (PAD_NF) only sets the pull. For PCIe reset, we now need to be able to set it to its native function (PCIE_RST_L), and drive it low, then high. BUG=b:182805349 TEST=Configure GPIO, see correct behavior. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I636371517c99f94f76834abc4575795d51aa0368 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55652 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-16timestamp,amd/common/apob_cache: Add timestamps for APOBRaul E Rangel
Updating the APOB takes a considerable amount of time. I decided to be granular and split out the operations so we know when we read vs read + erase + write. BUG=b:179092979 TEST=Boot guybrush and dump timestamps 3:after RAM initialization 3,025,425 (44) 920:starting APOB read 3,025,430 (5) 921:starting APOB erase 3,025,478 (48) 922:starting APOB write 3,027,727 (2,249) 923:finished APOB 3,210,965 (183,238) 4:end of romstage 3,210,971 (6) Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I08e371873112e38f623f452af0eb946f5471c399 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55401 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-16soc/amd/common/block/acpi/bert: fix NULL checkFelix Held
In acpi_soc_get_bert_region after the bert_errors_region call is was checked if the region parameter is NULL after the call; since region is a parameter of acpi_soc_get_bert_region, it's non-NULL. What we should be checking here is if region points to a non-NULL pointer. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reported-by: Coverity (CID:1457506) Change-Id: I0523504d65725ab2d2df4db28a5dedd90697b917 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55541 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-14soc/amd/common/pi/agesawrapper: use IOAPIC ID definesFelix Held
Part of the soc/amd/stoneyridge code already uses the FCH_IOAPIC_ID and GNB_IOAPIC_ID defines. Use those defines in the remaining location to make sure that the IOAPIC IDs are always consistent between the hardware register, the MADT and the IVRS ACPI tables. TEST=Timeless build of amd/gardenia results in identical binary. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I410a6560de66889b153c8a66b8dc5474ac114ba7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55429 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2021-06-13soc/amd/picasso: Move Type 17 DMI generation to commonNikolai Vyssotski
Move dmi.c code to common/fsp to be shared among different SOCs. BUG=b:184124605 Change-Id: I46071556bbbbf6435d9e3724bba19e102bd02535 Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52746 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-06-08soc/amd: factor out acpi_soc_get_bert_region to amd/commonFelix Held
This also adds BERT table gerenation support for Cezanne, but since the functionality to populate the BERT memory region isn't implemented yet, this won't result in a BERT table being generated on Cezanne, since bert_generate_ssdt will always return false there. TEST=BERT ACPI table generation still works on AMD/Mandolin Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I69b4a9a7432041e1f4902436fa4e6dee5332dbd2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55056 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-06-07soc/amd/common/fsp/pci: Add size field to PCIe interrupt routing HOBNikolai Vyssotski
EDK2 mandates HOB to be in increments of qword (8). This HOB has 13 elements which causes it be padded with 4 bytes of garbage. This results in coreboot failing intermittently with invalid data. Add "number of entries" field to specify the number of valid entries in the table. BUG=b:190153208 Cq-depend: chrome-internal:3889619 TEST=verify HOB is present and correct size (13) is reported Change-Id: Iaafae304f04a5f26d75a41a6d6fcb4ee69954d20 Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55237 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-07cezanne/psp_verstage: add reset/timer svcKangheui Won
The new cezanne PSP release added support for these svcs. So add those functionality back to cezanne psp_verstage. BUG=b:187906425 Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: Id542f5ed0762f582ea966466d67ed938ecb9c1f0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55137 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-06-07psp_verstage: initialize i2c in soc_initKangheui Won
GSC is connected with AP via i2c bus so we need to enable i2c in psp_verstage. Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: I5f7b73be67a692ea7de31ae53bd111d0e4b6998c Reviewed-on: https://review.coreboot.org/c/coreboot/+/55136 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-30soc/amd/common/block/espi: Explicitly assert PLTRST#Raul E Rangel
PLTRST# is currently asserted and latched when eSPI_RST# gets asserted. If eSPI_RST# isn't used on a platform or it doesn't properly assert in all cases, then PLTRST# will never be asserted. This could result in the AP and EC being out of sync. BUG=b:188188172, b:188935533 TEST=Warm reset guybrush with partial #22 rework. Verify that peripheral channel is correctly reset. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I20d12edf3efc6100096e24aa8d1aec76bbde264f Reviewed-on: https://review.coreboot.org/c/coreboot/+/54884 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-05-28soc/amd/picasso: fix MCACHE on psp_verstage RO bootKangheui Won
On RW boot path psp_verstage call cbfs_map which calls chain of _cbfs_alloc, cbfs_boot_lookup and cbfs_get_boot_device. Then cbfs_get_boot_device initializes MCACHE which is used later. However on RO boot path psp_verstage doesn't try to find anything in the CBFS which results RO MCACHE not to be initialized. Add cbfs_get_boot_device(true) to explicitly initialize MCACHE on recovery boot. BUG=b:177091575 BRANCH=none TEST=build and boot jelboz Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: I6c4b522fef5a4affd215faa122bdf6b53190cf3d Reviewed-on: https://review.coreboot.org/c/coreboot/+/54711 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-27soc/amd/common/block: Fix missing include in acp.hRaul E Rangel
We were missing the stdint.h header, and the header was sorted incorrectly in chip.h BUG=non TEST=build guybrush Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I209d3c9c48e5b06b2a56759af51cf2858eb99f51 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54922 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-05-26soc/amd/common/block/espi: Fix typo in espi_setup_periph_channelRaul E Rangel
ESPI_SLAVE_CHANNEL_READY is a read-only bit from the host perspective. It is set when the eSPI peripheral has configured the channel. We actually want to set the ESPI_SLAVE_CHANNEL_ENABLE flag. This never caused an issue before because the peripheral channel is enabled by default after PLTRST# is deasserted. This does fix the case where periph_ch_en == 0. It now properly clears the enable flag. BUG=b:188188172, b:188935533 TEST=Boot guybrush to OS, perform warm reset Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I24e0734d5652601ae9c967da528fec5e3f780991 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54883 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-05-25soc/amd/common/block/espi: Increase ESPI_CH_READY_TIMEOUT_US to 10msRaul E Rangel
The ChromeEC might take longer than 1ms for the peripheral channel to be enabled. The PLTRST# interrupt handler takes about ~539us. This doesn't account for the time it takes for the interrupt handler to be scheduled. Increasing the timeout to 10ms gives ample time. BUG=b:188188172, b:188935533 TEST=Boot guybrush and no longer see channel enable errors Suggested-by: Rob Barnes <robbarnes@google.com> Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ib6db577bf06175ceb17b446af706ad8c9f891481 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54788 Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-21soc/amd/cezanne,common,picasso: use BERT region reserved by FSP driverFelix Held
commit ce0e2a014009390c4527e064efb59260ef4d3a3b (drivers/intel/fsp2_0: use FSP to allocate APEI BERT memory region) adds a mechanism to reserve the BERT region inside the coreboot code, so we can get rid of the workaround to reserve it in the FSP and return the location in a HOB. mcfg->bert_size defaults to 0 which makes the FSP not generate the corresponding HOB, but that field is planned to be removed at least on Cezanne, so don't explicitly set it to 0. BUG=b:169934025 TEST=BERT table that gets generated in a follow-up patch for Picasso points to expected BERT region and Linux is able to access, decode and display it. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iaca89b47793bf9982181560f026459a18e7db134 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52584 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-20soc/amd/common: Show espi init in logMartin Roth
BUG=None TEST=See espi init messages in the log. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I9f856402ed9a026427d3529e6d61450b0623fe48 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54637 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-19soc/amd/common/block/espi_util: Work around in-band reset race conditionRaul E Rangel
When performing an in-band reset the host controller and the peripheral can have mismatched IO configs. i.e., The eSPI peripheral can be in IO-4 mode while, the eSPI host will be in IO-1. This results in the peripheral getting invalid packets and thus not responding. This causes the NO_RESPONSE status bit to be set and cause eSPI init to fail. If the peripheral is alerting when we perform an in-band reset, there is a race condition in espi_send_command. 1) espi_send_command clears the interrupt status. 2) eSPI host controller hardware notices the alert and sends a GET_STATUS. 3) espi_send_command writes the in-band reset command. 4) eSPI hardware enqueues the in-band reset until GET_STATUS is complete. 5) GET_STATUS fails with NO_RESPONSE and sets the interrupt status. 6) eSPI hardware performs in-band reset. 7) espi_send_command checks the status and sees a NO_RESPONSE bit. As a workaround we allow the NO_RESPONSE status code when we perform an in-band reset. BUG=b:186135022 TEST=suspend_stress_test and S5->S0 tests on guybrush and zork. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I71271377f20eaf29032214be98794e1645d9b70a Reviewed-on: https://review.coreboot.org/c/coreboot/+/54070 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-05-18cpu/x86: Only include smm code if CONFIG_HAVE_SMI_HANDLER=yArthur Heymans
This removes the need to include this code separately on each platform. Change-Id: I3d848b1adca4921d7ffa2203348073f0a11d090e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46380 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-05-13soc/amd: factor out acpigen_write_alib_dptc to common codeFelix Held
Also drop unneeded intermediate cast to void * before casting the address of the struct dptc_input type variables to uint8_t *. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie1e2aa1ec728a4e16d3a587d7400cdfc8962f443 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54077 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-05-12psp_verstage: remove not-implemented files for cezanneKangheui Won
Cezanne PSP is missing implementations for some svc apis. Do not include files related to missing svc apis. This CL should be reverted after the cezanne PSP supports these functions. BUG=b:187906425 Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: Ibaab4e8435624d403ef18e980146ebfd1598b61b Reviewed-on: https://review.coreboot.org/c/coreboot/+/53905 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-05-12soc/amd/{common,picasso}: Use common PCIE_GPP_DRIVER driverRaul E Rangel
This will change the names of the GPP bridges, but this ok since there is no hand written ASL that references these names. BUG=b:184766519 TEST=Boot picasso and dump ACPI Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ic09200156e8a37bd1a29ca95a17c8f8ae2b92bd3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54028 Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-12soc/amd/common/block/pci: Capitalize PCI ACPI namesRaul E Rangel
Lowercase characters are not valid ACPI identifiers. BUG=b:184766519 TEST=Boot picasso to OS and verify ACPI errors are no longer printed. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I75aca67f4607e97ced8ac00ac68e51c359aff944 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54027 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2021-05-12soc/amd{common,cezanne}: Move pcie_gpp.c to commonRaul E Rangel
Cezanne and Picasso can now use the same driver. BUG=b:184766519 TEST=Boot guybrush and dump ASL. Verified it didn't change. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ie4ede82935d6c69b323c1fdceaa61e306aa2820a Reviewed-on: https://review.coreboot.org/c/coreboot/+/54026 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2021-05-10soc/amd/picasso: move acpigen_dptc_call_alib to new common alibFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib0f7da12429b6278d1e4bc5d6650c7ee0f3b5209 Reviewed-on: https://review.coreboot.org/c/coreboot/+/53940 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-05-10Revert "soc/amd/common/espi: Don't set alert pin in espi_set_initial_config"Raul E Rangel
This reverts commit 6eced03b25954e370e20e62f2cbe41f9d5626eae. This prevents zork from booting. We get the following error: eSPI cmd0-cmd2: 00080009 00000000 00000000 data: 00000000. Error: unexpected eSPI status register bits set (Status = 0x10000010) Error: Slave GET_CONFIGURATION failed! This isn't a pure revert. It is more of a fix that keeps the old behavior. BUG=b:187122344 TEST=Boot zork an no longer see eSPI error Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: If75a35d3994b0fd23945a450032d3cc81abeb136 Reviewed-on: https://review.coreboot.org/c/coreboot/+/53932 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-10psp_verstage: differentiate bios entryKangheui Won
AMDFW tool stores bios dir entry to bios1_entry in picasso but bios3_entry in cezanne. Separate getting bios_dir_addr into a function and implement it on each platforms. Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: Ie18ed7979a04319c074b9b251130d419dc7f22dc Reviewed-on: https://review.coreboot.org/c/coreboot/+/52964 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-09soc/amd/common/fsp/pci: Add helper methods for PCI IRQ tableRaul E Rangel
These are helper methods for interacting with the AMD_FSP_PCIE_DEVFUNC_REMAP_HOB_GUID. BUG=b:184766519, b:184766197 TEST=Build guybrush Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Id03d0b74ca12e7bcee11f8d13b0e802861c13923 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52911 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-05-09soc/amd/common/block/pci: Implement acpigen_write_pci_{GNB,FCH}_PRTRaul E Rangel
This is loosely based off of picasso/pcie_gpp.c. This version uses the acpigen_write_PRT_X methods to write the actual records. There are also two functions, 1 for using the GNB, and one for using the FCH. The FCH one is useful when the GNB IO-APIC has not been initialized. BUG=b:184766519 TEST=Dump guybrush ACPI and verify it looks correct Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I926430074acb969ceb11fdb60ab56dcf91ac4c76 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52917 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-05-09soc/amd/{picasso,common/blocks/pci}: Move populate_pirq_dataRaul E Rangel
The method now dynamically allocates the pirq structure and uses the get_pci_routing_table method. BUG=b:184766519 TEST=Build guybrush and verify picasso SSDT has not changed. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I297fc3ca7227fb4794ac70bd046ce2f93da8b869 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52913 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-05-09soc/amd/common/block/pci: Introduce struct pci_routing_infoRaul E Rangel
This struct is similar to `struct pci_routing` defined in picasso/pcie_gpp.c. It additionally contains the irq used for the bridge and is structured in a way that the FSP can provide via HOB. The next set of CLs will migrate the pci routing functions used by picasso into common and enable pci routing table generation for cezanne. BUG=b:184766519 TEST=Build guybrush Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I1a8d988d125f407f0aa7bc1722d432446aa9aff8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/53922 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-05-08soc/amd/picasso/acpi/cpu: move WAL1 method that calls ALIB to commonFelix Held
TEST=Mandolin still boots into Linux and there's no ACPI warning in dmesg. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I7e6d38ebeae5e55a4a65930b989838532ab9c446 Reviewed-on: https://review.coreboot.org/c/coreboot/+/53920 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-08soc/amd/picasso,common: move ALIB DPTC parameter struct to common codeFelix Held
Also add an alib_ prefix to avoid possible name collisions. TEST=Timeless build for Mandolin results in identical binary. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib0f220a4cde6da764bb8bc589b5f44ae16496bd7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/53918 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-08soc/amd/picasso,common: move ALIB DPTC IDs to common codeFelix Held
These parameter IDs are defined in the AGESA Interface specification #55483. This patch also adds a ALIB_DPTC_ prefix to the IDs and makes the names more consistent. TEST=Timeless build for Mandolin results in identical binary. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I75e0504f6274ad50c53faa8fcbde4d6821d85a04 Reviewed-on: https://review.coreboot.org/c/coreboot/+/53917 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-08soc/amd: factor out ACPI ALIB function numbers to common codeFelix Held
The ACPI ALIB function numbers are defined in the AMD Generic Encapsulated Software Architecture (AGESA™) Interface Specification (document #55483). TEST=Timeless build stays the same for Mandolin (Picasso) and Gardenia (Stoneyridge). Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I290ef0db32c65ebb2bbbe4f65db4df772b884161 Reviewed-on: https://review.coreboot.org/c/coreboot/+/53915 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-07soc/amd/common/acpi/pci_int.asl: Allow IRQ sharingRaul E Rangel
PCI interrupts are level active low, so they can be shared. BUG=b:184766519 TEST=Boot guybrush to OS with `pci=nomsi amd_iommu=off noapic` Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I439337dd66fe56790406c6d603e73512c806a19d Reviewed-on: https://review.coreboot.org/c/coreboot/+/52957 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-07soc/amd/common: Add Kconfig/Makefile support for common/fsp/*Raul E Rangel
This will allow us to have subdirectories in common/fsp. BUG=b:184766519 TEST=Build guybrush Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ib3497791e1963867c8fe06a42c111e5d0503ade1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52910 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-05-06soc/amd/common/espi,mb/: Allow configuring open drain ALERT#Raul E Rangel
Some designs might wish to use an open drain eSPI ALERT#. This change adds an enum that allows setting the eSPI alert mode. BUG=b:187122344, b:186135022 TEST=Boot guybrush using all 3 alert modes Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ia35fc59a699cf9444b53aad5c9bb71aa27ce9251 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52954 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-05-06soc/amd/common/espi: Don't set alert pin in espi_set_initial_configRaul E Rangel
The eSPI spec says that the Alert Mode defaults to in-band on reset. This change ensures the controller is in sync with the eSPI peripheral. The configured alert mode is configured in espi_set_general_configuration. BUG=b:187122344, b:186135022 TEST=Boot guybrush and make sure we don't get any eSPI errors. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ib43e190d08d77ecfcd22ead2bf42e5de2202b555 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52953 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Rob Barnes <robbarnes@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-06soc/amd/common/espi: Print set eSPI peripheral configRaul E Rangel
This will print the config we are setting on the eSPI peripheral. e.g., Setting general configuration: slave: 0x98a00000 controller: 0xe2000000 eSPI Slave configuration: CRC checking enabled Dedicated Alert# used to signal alert event eSPI quad IO mode selected Only eSPI single IO mode supported Alert# pin is open-drain eSPI 33MHz selected eSPI up to 20MHz supported Maximum Wait state: 0 BUG=b:187122344, b:186135022 TEST=Boot guybrush Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I1a2382d8ab3d3f0d14a139c57470cb895112eca9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52952 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-06soc/amd/{common/picasso}: Move pci_int.aslRaul E Rangel
We can share this with cezanne. BUG=b:184766519 TEST=Build picasso Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: If746d55345f6b7c828376b64adc5532d20413f68 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52916 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-06soc/amd/{picasso/common}: Move populate_pirq_data prototype to commonRaul E Rangel
This method signature will also be used by cezanne, so move it to common. BUG=b:184766519 TEST=Build picasso Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I421bdad51776278f83148174e6f72bdc38249e54 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52912 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-05-05soc/amd/common/fsp/fsp-acpi: add check for maximum table sizeFelix Held
If the ACPI table size in the HOB data header is larger than the maximum HOB payload, don't add the table at all and print an error instead, since in this case the memcpy would read past the end of the HOB data structure. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I965c01bd9ab66b14d6f77b6f23c28479ae6d6a50 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52897 Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-05soc/amd/common/fsp/fsp-acpi: factor out SSDT from HOB functionalityFelix Held
This function will be reused in Cezanne, so move it from the Picasso directory to the common FSP integration code. TEST=On Mandolin Linux finds the AMD SSDT that contains ALIB. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I7b256de712fe60d1c021cb875aaadec1d331584b Reviewed-on: https://review.coreboot.org/c/coreboot/+/52896 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-05-02soc/amd/cezanne: add verstage filesKangheui Won
Add support for psp_verstage compilation. Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: Iac48c92a787adabfdaec96b6e8d2e24708d7e652 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52752 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-04-30soc/amd/common: Move external oscillator config away from commonKarthikeyan Ramasubramanian
The usage of external oscillator has got nothing to do with Audio Co-processor (ACP). Hence move it out of common config and put it into the SoC config where it is being used. BUG=None TEST=Build Dalboz and Vilboz mainboards. Change-Id: I8c5d98addfba750f9ddb87a846599541b4a8340a Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52771 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-29soc/amd/common: Remove eSPI decode workaroundRaul E Rangel
We no longer lock up if we clear the port 80 bit. I'm assuming this was fixed when we configured the PSP to no longer setup eSPI. BUG=b:183974365 TEST=Boot guybrush to OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I1530d08974d42e0b06eb783521dea32fca752d85 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52677 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2021-04-29psp_verstage: make temp_stack optionalKangheui Won
Temp stack for verstage is only needed for picasso, so make it optional in the layout file. Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: I44196103a3531e9d01c96ab8f454c8b580fe9807 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52688 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-04-29psp_verstage: make get_max_workbuf_size optionalKangheui Won
From cezanne we have enough space in PSP so we don't have to worry about workbuf size. Hence the function only exists in picasso and deprecated for later platforms. So wrap svc_get_max_workbuf_size and provide default weak function so future platforms don't have to implement dumb function for it. TEST=build and boot zork, check weak function is not called in zork Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: I16e8edf8070aaacb3a6a6a8adc92b44a230c3139 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52687 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-04-29soc/amd/picasso: move PSP_SRAM addrs to separate headerKangheui Won
These addresses will be changed in cezanne. Before start working on cezanne, move these out to separate header as a clean-up. TEST=emerge-zork coreboot Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: I2499281d250aae701f86bfcc87c7681e5b684b6a Reviewed-on: https://review.coreboot.org/c/coreboot/+/52625 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-29soc/amd/common/acp: Move Audio Co-processor driver to commonKarthikeyan Ramasubramanian
Audio Co-processor driver is similar for both Picasso and Cezanne SoCs. Hence move it to the common location. BUG=None. TEST=Builds Dalboz, Trembyle, Vilboz, Mandolin and Bilby mainboards. Change-Id: I91470ff68d1c183df9a2927d71b03371b535186a Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52643 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-28soc/amd/common/smi_handler: Print warning when receiving an SCI SMIRaul E Rangel
We don't have any infrastructure setup to handle SCI SMIs. Instead of just silently ignoring the SMI, print a warning saying that it is being ignored. BUG=none TEST=Trigger an SCI SMI and see warning printed. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I803e572250925b7d5ffdbb3e8958f9aff1f808df Reviewed-on: https://review.coreboot.org/c/coreboot/+/52674 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-23soc/amd/common/block/include/amdblocks: add msr_zen.hFelix Held
Add defines for the Machine Check Architecture Extensions (MCAX) MSRs and the new MCA_CTL_MASK MSRs. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id78483e7df00c3e99c698c0344f38be68d1dfb72 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52615 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-04-23amd/common/blocks: Print eSPI peripheral channelRaul E Rangel
BUG=none TEST=Boot guybrush with ESPI_DEBUG Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I4312aaedcfed1535ef00a4686f218d30e351b33f Reviewed-on: https://review.coreboot.org/c/coreboot/+/52226 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-23amd/vboot: remove bl_syscall_public.h from includeKangheui Won
bl_syscall_public.h is a header file for PSP app, but was used for x86 code to get the definition of PSP_INFO. Move the definition into psp_transfer.h and do not include bl_syscall_public.h from x86 code. BUG=none TEST=build psp_verstage on zork BRANCH=none Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: I0fe011652a47d0ba2939dc31ee3b83f0718a61dc Reviewed-on: https://review.coreboot.org/c/coreboot/+/52537 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-22soc/amd/common/block/cpu/noncar/memmap: include types.hFelix Held
size_t is used in the code, so we should include types.h instead of stdint.h to also have those type definitions. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I04c50de257a2d6982bfd4907eb5a1325a751919a Reviewed-on: https://review.coreboot.org/c/coreboot/+/52582 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-21soc/amd/{cezanne,common}/acpi: Add _OSC methodRaul E Rangel
The linux kernel requires a valid _OSC method. Otherwise the _LPI table is ignored. See https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/third_party/kernel/v5.10/drivers/acpi/bus.c;l=324 Before this patch: acpi_processor_get_lpi_info: LPI is not supported After this patch: acpi_processor_evaluate_lpi: ACPI: \_SB_.CP00: ACPI: Found 4 power states BUG=b:178728116 TEST=Boot OS and verify _LPI table is parsed Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I44e554b9db6f70fdd1559105cdaee53aeb2bfbf5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52528 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-04-20soc/amd/{common,cezanne}: Add uPEP deviceRaul E Rangel
The uPEP device is required to support S0i3. The device has been written in ASL to make it easier to read and maintain. The device constraints are purely informational. We use a dummy constraint like the Intel platforms to keep both linux and Windows functional. In order for this device to be used by the linux kernel the ACPI_FADT_LOW_PWR_IDLE_S0 flag must be set. So including it unconditionally doesn't cause any problems. The AMD Modern Standby BIOS Implementation Guide defines two UUIDs, one for getting the device constraints, and one for handling notifications. This differs from the Intel specification and the linux driver implementation. For this reason I haven't implemented any of the notification callbacks yet. BUG=b:178728116 TEST=Boot OS and verify _DSM is called: [ 0.226701] lps0_device_attach: ACPI: \_SB_.PEP_: _DSM function mask: 0x3 [ 0.226722] lpi_device_get_constraints_amd: ACPI: \_SB_.PEP_: _DSM function 1 eval successful [ 0.226723] lpi_device_get_constraints_amd: ACPI: \_SB_.PEP_: LPI: constraints list begin: [ 0.226724] lpi_device_get_constraints_amd: ACPI: \_SB_.PEP_: LPI: constraints list end Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I2deef47eabe702efe1a0f3747c9f27bcec37464b Reviewed-on: https://review.coreboot.org/c/coreboot/+/52445 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-16psp_verstage: move svc to platform-specific dirKangheui Won
Since there are some differences between picasso PSP svc and cezanne PSP svc, each platform should have their own svc wrapper. Moreover cezanne PSP will drop unused parameters from update_psp_bios_dir and save_uapp_data so make wrapper around it. BUG=b:182477057 BRANCH=none TEST=build psp_verstage and boot on zork Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: I69f998865fc3184ea8900a431924a315c5ee9133 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52307 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-16soc/amd: move psp_verstage to amd/commonKangheui Won
psp_verstage is not specific to picasso. There might be picasso-specific code but move everything into common as a first step. While developing psp_verstage for cezanne picasso-specific code will move back to picasso directory. BUG=b:182477057 BRANCH=none TEST=build psp_verstage on zork Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: Ifb1df0d82b972f28be2ffebd476c2553cbda9810 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52306 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-04-16soc/amd/common: Correct Kconfig enable for ACPI GPIO functionsMartin Roth
The Kconfig value specified Intel instead of AMD. BUG=b:184198808 TEST=Backlight enabled in the OS Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I9fbdf821591ec886f383c1a5ac197f8f213c4cc4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52384 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-15soc/amd/common/block/gpio_banks: Use configure_scimap()Kyösti Mälkki
There is no need to stash the SCI trigger register configuration and apply it at the end. Remove this to make SCI and SMI programming more symmetrical and to use available configure_scimap function instead of implementing it again, but without the additional checks. Using this function also allows removing soc_route_sci. Change-Id: Ie23da79546858282910db65182a6315ade506279 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43012 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-04-14soc/amd/common/block/pm: rework pm_set_power_failure_stateFelix Held
Picasso and Stoneyridge didn't do a read-modify-write operation on the lower nibble of PM_RTC_SHADOW_REG, but just wrote the upper nibble as all zeros. Since the upper nibble might be uninitialized before the lower nibble gets written, do what Picasso and Stoneyridge did here instead of what the reference code does. Also add a comment why and how this register behaves a bit weird. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0bda2349e3ae84cba50b187cc773fd8a5b17f4e2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52301 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-14soc/amd/common/block/pm: remove POWER_STATE_DEFAULT_ON_AFTER_FAILUREFelix Held
Not selecting POWER_STATE_DEFAULT_ON_AFTER_FAILURE brings Cezanne that is currently the only SoC using this functionality in line with Picasso where the default is that the board remains in power off mode after power was lost and later restored. Boards can change this behavior by selecting POWER_STATE_OFF_AFTER_FAILURE, POWER_STATE_ON_AFTER_FAILURE or POWER_STATE_PREVIOUS_AFTER_FAILURE. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic96f40e3c9867cd821e58d752f58b763930f6d0f Reviewed-on: https://review.coreboot.org/c/coreboot/+/52300 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-14soc/amd/common/block/pm: select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILUREFelix Held
Without this being selected, mainboards can't select MAINBOARD_POWER_STATE_PREVIOUS to use the power state restoration code path in pmlib.c Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I753659fa753e03a66b6c6b2eb97e7ef20c71ca57 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52299 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-14soc/amd/picasso/romstage: factor out chipset state saving functionalityFelix Held
Since Cezanne needs the exact same code, move it to the common directory and add a Kconfig option to add this functionality to the build. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I04c4295071a3df7afcb4dfd5435b11fb0bf6963f Reviewed-on: https://review.coreboot.org/c/coreboot/+/52272 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-11soc/amd/common/block/gpio: remove SoC type check in gpio_fill_wake_stateFelix Held
Verified that all accessed registers exist in all SoCs that use this code (Carrizo, Mullins, Stoneyridge, Picasso and Cezanne at the moment) and that the bit definitions match as well. Also at the time of writing this patch only Picasso calls gpio_fill_wake_state, so dropping the check won't change behavior. This also avoids having SoC specific code that doesn't get selected by Kconfig options in the common AMD SoC directory and also avoids having to add a check for SOC_AMD_CEZANNE to support this functionality on Cezanne in a follow-up patch. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If770780a67776daf81744db1b635ffd402653a47 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52223 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-10soc/amd/common: Handle power resume after power failureKarthikeyan Ramasubramanian
Introduce a power management library to handle the power resume after power failure. Enable HAVE_POWER_STATE_AFTER_FAILURE config when this library is enabled. BUG=b:183739671 TEST=Build Guybrush and Majolica mainboard. Change-Id: Iea4ea57d747425fe6714d40ba6e60f2447febf28 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51924 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-04-10soc/amd/cezanne: Add GRXS and GTXS methodEric Lai
Add GRXS and GTXS support. Move the gpio method into common place. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I8ba377179d6976cf26ed0dc521d8e4eff051dc85 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52202 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-04-08soc/amd: remove special GPIO_2 override soc_gpio_hookKyösti Mälkki
This override was added to have the SCI mapping configured if GPIO was used as WAKE_L pin. This however didn't set up the SCI level and trigger information, so it likely never worked as intended. Change-Id: I44661f05c8f517ece88714c625603579731d174b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43049 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-04-08soc/amd/common: Add PM_ESPI_INTR_CTRLRaul E Rangel
This register is used for masking/unmasking eSPI IRQs. BUG=none TEST=Build guybrush Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ia209539b2e0ce390e227757b16c2969b9124a845 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52142 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Rob Barnes <robbarnes@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-05soc/amd/common: Add some ESPI register definitionsMartin Roth
Use definitions instead of magic numbers clean up some whitespace while I'm here. BUG=b:183207262 TEST=Build Change-Id: Ieae53b12e5303641fb3f180c47468aaa6906e9af Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51747 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-04-05soc/amd: Make espi_clear_decodes privateRaul E Rangel
espi_setup already clears most of the controller registers. So this change consolidates the clear logic into one spot. This shouldn't result in a behavior change on Picasso. Picasso already has the eSPI decodes clear on boot, so this change is a nop. BUG=b:183524609 TEST=Boot guybrush to the OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ic57689e50febd29796d8ac8d99c81e41fee5b41c Reviewed-on: https://review.coreboot.org/c/coreboot/+/52064 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-04-05soc/amd: Make espi_configure_decodes privateRaul E Rangel
This is only ever called after espi_setup. 55861 - AMD System Peripheral Bus Overview also says that io ranges should be configured before enabling the BUS_MASTER bit. BUG=b:183524609 TEST=Boot guybrush to OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I074e487d8768a578ee889a125b9948e3aa6c7269 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52059 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-04-05soc/amd/common/espi: Clear DNCMD_COMPLETE on completionRaul E Rangel
Tidy up the interrupt status. This will leave SLAVE0_INT_STS = 0. BUG=b:183524609 TEST=Boot guybrush to OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I950cfb81521e35758c120a482670cfdb924201d2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52056 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-05soc/amd/common/espi: Reset eSPI registers to known stateRaul E Rangel
This sets the eSPI registers to the reset values specified in the PPR. On Cezanne, the PSP modifies these registers such that the eSPI peripheral cannot send DEFER packets. This causes random bus errors. These reset values are identical to what is currently used on Zork. I didn't clear out ESPI_DECODE because it's currently being done by cb:51749. BUG=b:183524609 TEST=Boot guybrush to the OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ic3a9860747aac78121358b4499d8a38052236c0c Reviewed-on: https://review.coreboot.org/c/coreboot/+/52058 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-04-05soc/amd/common/espi: Add missing eSPI register definitionsRaul E Rangel
These are defined in the public Picasso PPR - 55570-B1 Rev 3.15. BUG=b:183524609 TEST=Build guybrush Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I7e601f767327e0a24a086146623af039388b2e7b Reviewed-on: https://review.coreboot.org/c/coreboot/+/52057 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Rob Barnes <robbarnes@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-05soc/amd/common/espi: Add ESPI_ prefix to SLAVE0_INT_ENRaul E Rangel
This matches the other register definitions. BUG=b:183524609 TEST=Build guybrush Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I0ed92add633f294f92c6a0dde32851d01b10db3c Reviewed-on: https://review.coreboot.org/c/coreboot/+/52055 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-04-05soc/amd/common: Add func to clear eSPI IO & memory decode rangesMartin Roth
Previously, the eSPI code would only add to existing decode ranges, and there wasn't any way to clear ranges. This clears all the ranges so the eSPI configuration can start fresh. BUG=b:183207262, b:183974365 TEST=Verify on Guybrush Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: Ic4e67c40d34915505bdd5b431a064d2c7b6bbc70 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51748 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-31soc/amd/common/block/graphics: Don't add VBIOS to cbmem when using GOPRaul E Rangel
pci_rom_ssdt reloads the oprom from cbfs. It then places it into cbmem and writes the offsets as the ROM ACPI node. The GOP driver modifies the VBIOS so we don't want to reread from cbfs. When using GOP we also pass the offsets with the VFCT table. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Iaf53e750564f1f0e115cd354790da62e672d74b7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51541 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Martin Roth <martinroth@google.com>
2021-03-29soc/amd: smbus: Use correct type for uintptr_tPaul Menzel
Fix the format warning below by using `PRIxPTR`, which is defined as unsigned long. src/soc/amd/common/block/smbus/smbus.c:33:56: error: format specifies type 'size_t' (aka 'unsigned int') but the argument has type 'uintptr_t' (aka 'unsigned long') [-Werror,-Wformat] printk(BIOS_ERR, "Invalid SMBus or ASF base %#zx\n", mmio); ~~~~ ^~~~ %#lx src/include/console/console.h:60:61: note: expanded from macro 'printk' #define printk(LEVEL, fmt, args...) do_printk(LEVEL, fmt, ##args) ~~~ ^~~~ 1 error generated. Change-Id: I727c490d3097dcf36cdbcd4db2852cd49d11785f Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51843 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-03-29soc/amd/common/block/acpimmio/mmio_util: add fch_disable_kb_rstFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Kangheui Won <khwon@chromium.org> Change-Id: Ie65e39ffb8c353415f5b68e1e0f378d18eeb7498 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51784 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-29soc/amd: move PM_RST_CTRL1 register definition to common acpimmio headerFelix Held
TEST=Verified that this register and the defined bits exist in Cezanne, Picasso, Stoneyridge, Bolton and SB800. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I32d1d577b05edab006981516a5aefd822e7b984a Reviewed-on: https://review.coreboot.org/c/coreboot/+/51783 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-28soc/amd/common/gpio: add PAD_NF_SCI pad typeFelix Held
This patch adds a pin configuration macro that supports both switching a pin to its native function and configuring it as a SCI source. This is a preparation to remove the GPIO2 soc_gpio_hook. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If0da5c010f35fd902f6b8857368daec93c12394a Reviewed-on: https://review.coreboot.org/c/coreboot/+/50373 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-28soc/amd/common/block/i2c: Use `size_t` for `num_pins`Angel Pons
There's no need to use a fixed-width type here. Change-Id: I727c64661990040db356c5508fecc0a65960c095 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51794 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-28soc/amd/common/block/i2c: Fix printf format specifiersAngel Pons
The correct printf format specifier for an `unsigned int` is `%u`. Change-Id: Iaf780eb366f8c3493b89beb9a5643fa285e7825d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51793 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-25soc/amd/common/block/i2c: fix control flow bugFelix Held
commit 4f87ae1d4a3a597f1260534001bd99160cc8ca99 introduced a regression in the I2C initialization resulting in soc_i2c_misc_init never getting called, since the continue statement was indented like it belonged to the if above, but due to the missing curly braces it was outside the if block. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Found-by: Coverity CID 1451395, 1451387 Change-Id: Id1f17ad59cba44e96881f5511df303ae90841ab3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51786 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-25soc/amd/common/block/gpio_defs: Wake from either S0i3 or S3Karthikeyan Ramasubramanian
Add a helper bit mask to enable wake from either S0i3 or S3. BUG=None TEST=Build the Guyrbush mainboard. Change-Id: I934abad78135260081a61aee4c496b362e483de1 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51745 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-13 10:34:38 +0000