summaryrefslogtreecommitdiff
path: root/src/soc/amd/common/fsp
AgeCommit message (Collapse)Author
2021-11-11arch/x86: Refactor the SMBIOS type 17 write functionSubrata Banik
List of changes: 1. Create Module Type macros as per Memory Type (i.e. DDR2/DDR3/DDR4/DDR5/LPDDR4/LPDDR5) and fix compilation issue due to renaming of existing macros due to scoping the Memory Type. 2. Use dedicated Memory Type and Module type for `Form Factor` and `TypeDetail` conversion using `get_spd_info()` function. 3. Create a new API (convert_form_factor_to_module_type()) for `Form Factor` to 'Module type' conversion as per `Memory Type`. 4. Add new argument as `Memory Type` to smbios_form_factor_to_spd_mod_type() so that it can internally call convert_form_factor_to_module_type() for `Module Type` conversion. 5. Update `test_smbios_form_factor_to_spd_mod_type()` to accommodate different memory types. 6. Skip fixed module type to form factor conversion using DDR2 SPD4 specification (inside dimm_info_fill()). Refer to datasheet SPD4.1.2.M-1 for LPDDRx and SPD4.1.2.L-3 for DDRx. BUG=b:194659789 TEST=Refer to dmidecode -t 17 output as below: Without this code change: Handle 0x0012, DMI type 17, 40 bytes Memory Device Array Handle: 0x000A Error Information Handle: Not Provided Total Width: 16 bits Data Width: 16 bits Size: 2048 MB Form Factor: Unknown .... With this code change: Handle 0x0012, DMI type 17, 40 bytes Memory Device Array Handle: 0x000A Error Information Handle: Not Provided Total Width: 16 bits Data Width: 16 bits Size: 2048 MB Form Factor: Row Of Chips .... Change-Id: Ia337ac8f50b61ae78d86a07c7a86aa9c248bad50 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56628 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-02lib: Add new argument as `ddr_type` to smbios_bus_width_to_spd_width()Subrata Banik
Add DDR5 and LPDDR5 memory type checks while calculating bus width extension (in bits). Additionally, update all caller functions of smbios_bus_width_to_spd_width() to pass `MemoryType` as argument. Update `test_smbios_bus_width_to_spd_width()` to accommodate different memory types. Create new macro to fix incorrect bus width reporting on platform with DDR5 and LPDDR5 memory. With this code changes, on DDR5 system with 2 Ch per DIMM, 32 bit primary bus width per Ch showed the Total width as: Handle 0x000F, DMI type 17, 40 bytes Memory Device Array Handle: 0x0009 Error Information Handle: Not Provided Total Width: 80 bits Data Width: 64 bits Size: 16 GB ... BUG=b:194659789 Tested=On Alder Lake DDR5 RVP, SMBIOS type 17 shows expected `Total Width`. Change-Id: I79ec64c9d522a34cb44b3f575725571823048380 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58601 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-09-24soc/amd/common: factor out FSP-related parts of common KconfigFelix Held
TEST=Timeless build for Mandolin results in identical image. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib2fb6c29b9f42c00f252994ae2a40b7ff668105a Reviewed-on: https://review.coreboot.org/c/coreboot/+/57885 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-08-30soc/amd/common/fsp/Makefile: drop strip_quotes call in FSP-M size checkFelix Held
No need to strip the quotes of the FSP-M file path in the size check and it's always a good idea to not remove the quotes around file paths that will get passed as parameters to shell programs so that spaces in the path can't cause malfunction. TEST=All cases still behave as expected for Mandolin. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Nico Huber <nico.h@gmx.de> Change-Id: Ieeea84b5861f9d15b2472208432169dc8e3f0049 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57218 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-08-28soc/amd/common/fsp/Makefile: check if CONFIG_FSP_M_FILE is definedFelix Held
When CONFIG_FSP_M_FILE isn't defined, the parameter of the file-size call evaluates to an empty string, so the file-size call will run "cat | wc -c" which will cause make to get stuck in there. Also print a message when no FSP-M file is specified that the resulting image won't boot successfully. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6b02774e2c79d12554fd076aa01bbe972176f372 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57189 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-08-27soc/amd/common/fsp/fsp_validate: add runtime check for FSP-M binary sizeFelix Held
When modules are added to the FSP and they won't fit into the FSP binary any more, the size can be increased in the FSP build. Especially in the case of debug builds the increased size might not fit into the memory region it gets decompressed into which starts at FSP_M_ADDR and has a size of FSP_M_SIZE. SoCs can implement the soc_validate_fspm_header function that ends up being called by the FSP driver in romstage to do some additional checks on the FSP binary's header that includes the version number and the image size. We can use the image size field to check if it fits into the reserved region. Since the FSP-M memory region is located after romstage loading it won't clobber the romstage code where we do the check. This runtime check is added in addition to the build-time check to also cover the case when the FSP binaries in CBFS get replaced with ones that don't fit into the reserved memory region after the coreboot build. BUG=b:186149011 TEST=Mandolin still boots fine with the patch applied. When as a test the FSP_M_SIZE Kconfig option in soc/amd/picasso is decreased to 0x10000 which is by far not enough for the decompressed FSP-M binary to fit into it prints the newly added error message on the console and then stops. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I9b74a2d03993ba50b166eb6e87d4e57b93afc069 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57068 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-26soc/amd/common/fsp/Makefile: check if FSP-M is larger than FSP_M_SIZEFelix Held
The FSP-M binary needs to fit into the memory region that starts at FSP_M_ADDR and is FSP_M_SIZE bytes large, so error out during build time if the uncompressed FSP-M file is larger than the size of the region it will be copied into. BUG=b:186149011 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Furquan Shaikh <furquan@google.com> Change-Id: Ice4a59e5a723c3c0a40b1f3f3227aee6b9dcb39a Reviewed-on: https://review.coreboot.org/c/coreboot/+/57129 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-06-30soc/amd/common/fsp/dmi.c: Fix Type 17 DMI reportingNikolai Vyssotski
With two versions of *speed_mhz_to_reported_mts() we need to call the correct one based on the reported memory type. BUG=b:184124605 TEST="dmidecode --type 17" in OS on Guybrush Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Change-Id: I92e834097546e3ef7130830444a80f818bdea3d5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55852 Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-13soc/amd/picasso: Move Type 17 DMI generation to commonNikolai Vyssotski
Move dmi.c code to common/fsp to be shared among different SOCs. BUG=b:184124605 Change-Id: I46071556bbbbf6435d9e3724bba19e102bd02535 Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52746 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-06-07soc/amd/common/fsp/pci: Add size field to PCIe interrupt routing HOBNikolai Vyssotski
EDK2 mandates HOB to be in increments of qword (8). This HOB has 13 elements which causes it be padded with 4 bytes of garbage. This results in coreboot failing intermittently with invalid data. Add "number of entries" field to specify the number of valid entries in the table. BUG=b:190153208 Cq-depend: chrome-internal:3889619 TEST=verify HOB is present and correct size (13) is reported Change-Id: Iaafae304f04a5f26d75a41a6d6fcb4ee69954d20 Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55237 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-09soc/amd/common/fsp/pci: Add helper methods for PCI IRQ tableRaul E Rangel
These are helper methods for interacting with the AMD_FSP_PCIE_DEVFUNC_REMAP_HOB_GUID. BUG=b:184766519, b:184766197 TEST=Build guybrush Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Id03d0b74ca12e7bcee11f8d13b0e802861c13923 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52911 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-05-07soc/amd/common: Add Kconfig/Makefile support for common/fsp/*Raul E Rangel
This will allow us to have subdirectories in common/fsp. BUG=b:184766519 TEST=Build guybrush Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ib3497791e1963867c8fe06a42c111e5d0503ade1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52910 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-05-05soc/amd/common/fsp/fsp-acpi: add check for maximum table sizeFelix Held
If the ACPI table size in the HOB data header is larger than the maximum HOB payload, don't add the table at all and print an error instead, since in this case the memcpy would read past the end of the HOB data structure. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I965c01bd9ab66b14d6f77b6f23c28479ae6d6a50 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52897 Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-05soc/amd/common/fsp/fsp-acpi: factor out SSDT from HOB functionalityFelix Held
This function will be reused in Cezanne, so move it from the Picasso directory to the common FSP integration code. TEST=On Mandolin Linux finds the AMD SSDT that contains ALIB. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I7b256de712fe60d1c021cb875aaadec1d331584b Reviewed-on: https://review.coreboot.org/c/coreboot/+/52896 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-11soc/amd/picasso: move chipset_handle_reset to commonFelix Held
The FSP integration code needs this function to be present. It's not supposed to be called, but if it is, it'll print an error and call the SoC's cold reset function. Change-Id: I15f2622d9d9d0f22e3cf8e6283b578f5933b1a9f Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48537 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-11 08:49:47 +0000