| Age | Commit message (Expand) | Author |
|---|---|---|
| 2021-02-07 | soc/amd/cezanne/romstage: Store early dram region | Raul E Rangel |
| 2021-02-05 | soc/amd/cezanne: populate some FSP-M UPDs | Felix Held |
| 2021-01-30 | soc/amd/cezanne: add use result of acpi_is_wakeup_s3() in FSP calls | Felix Held |
| 2021-01-24 | soc/amd/cezanne: add basic romstage | Felix Held |
| 2021-01-24 | soc,vendorcode/amd/cezanne: add basic FSP integration | Felix Held |
| 2020-12-05 | soc/amd/cezanne: add skeleton for new SoC | Felix Held |
 |
index : coreboot.git | |
| my copy of coreboot | gitea |
| aboutsummaryrefslogtreecommitdiff |