coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2021-06-28	soc/amd/cezanne: Add call to mb to configure eSPI requirements	Martin Roth
2021-06-23	soc/amd/cezanne: Init eSPI early if required	Martin Roth
2021-04-10	soc/amd/cezanne: Set Power state after power failure	Karthikeyan Ramasubramanian
2021-04-05	soc/amd: Make espi_clear_decodes private	Raul E Rangel
2021-04-05	soc/amd: Make espi_configure_decodes private	Raul E Rangel
2021-04-05	soc/amd/cezanne: Clear eSPI ranges before configuring eSPI	Martin Roth
2021-03-29	soc/amd: add DISABLE_KEYBOARD_RESET_PIN option	Felix Held
2021-03-29	soc/amd/cezanne: Implement PROVIDES_ROM_SHARING	Raul E Rangel
2021-03-22	soc/amd/cezanne: Initialize I2C	Zheng Bao
2021-03-22	soc/amd/cezanne: Get I2C specific code for cezanne	Zheng Bao
2021-03-02	soc/amd/cezanne: Disable legacy DMA IO ports	Raul E Rangel
2021-02-24	soc/amd/cezanne: Add eSPI support	Zheng Bao
2021-02-09	soc/amd/cezanne: Enable early LPC support in bootblock stage	Zheng Bao
2021-01-14	soc/amd/cezanne: add AOAC support	Felix Held
2021-01-14	soc/amd/cezanne: add console UART support	Felix Held
2020-12-09	soc/amd/cezanne: add basic early FCH initialization to bootblock	Felix Held