coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2021-06-07	soc/amd/cezanne: Configure I2C Pad RX Select through devicetree	Karthikeyan Ramasubramanian
2021-05-27	soc/amd/cezanne: add devicetree setting for PSPP policy	Felix Held
2021-05-26	soc/amd/cezanne: add support for the changed AMD FSP API for USB PHY	Julian Schroeder
2021-05-19	soc/amd/cezanne/fch: add PCIe GPP clock generator configuration settings	Felix Held
2021-05-12	soc/amd/cezanne/chip.h: add DPTC and tablet mode options	Felix Held
2021-04-30	amd/cezanne: Add telemetry setting to UPD	Chris Wang
2021-04-26	soc/amd/cezanne: Update STAPM vars with units	Martin Roth
2021-04-26	amd/cezanne: Add slow_ppt_time & thermctl_limit to UPD	Martin Roth
2021-04-21	soc/amd/cezanne: add SMU settings to devicetree	Felix Held
2021-04-21	soc/amd/cezanne: add downcoring and SMT disable settings to devicetree	Felix Held
2021-04-21	soc/amd/cezanne/chip.h: include missing types.h	Felix Held
2021-04-16	soc/amd/cezanne: Add modern standby option to chip config	Mathew King
2021-03-22	soc/amd/cezanne: Get I2C specific code for cezanne	Zheng Bao
2020-12-06	soc/amd/cezanne: add config.c and minimal chip.h	Felix Held