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path: root/src/soc/amd/cezanne/chip.c
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2022-10-13soc/amd/*: Hook up device_operations in chipset.cbArthur Heymans
This removes the need for a lot of boilerplate code in the soc code to hook up device_operations to devices. Change-Id: I2afc1855407910f1faa9bdd4e9416dd46474658e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67738 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-13soc/amd/*: Move emmc disabling to device opsArthur Heymans
This allows for reduced use of chip_operations in the followup patch and allows the allocator to skip over the used mmio. Change-Id: I4052438185e7861792733b96a1298201c73fc3ff Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68113 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2021-08-29soc/amd/cezanne/chip: add functionality to power down eMMC interfaceFelix Held
Power down the eMMC controller via the AOAC interface when it's not enabled in the devicetree. BUG=b:184978118 TEST=On guybrush the unused eMMC controller is disabled in AOAC after applying this patch. Before this patch it was enabled. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I18f4626a29fdc422218777058341b0eae401bcd4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55537 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-05-05soc/amd/cezanne/agesa_acpi: add and call agesa_write_acpi_tablesFelix Held
This function will be used to add some SSDTs. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia88cb5ea483850a8659f3bae8040c82eb2735d26 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52902 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2021-04-16soc/amd/cezanne: Port ACPI p-state and c-state entries from picassoJason Glenesk
Add generate_cpu_entries to device operations. Add support to generate cpu p-state and c-state SSDT entries. BUG=b:184151560 TEST=Dump and verify SSDT entry for CPU p-states and c-states. Change-Id: I77d8078b94fb661dc045b4184955c8cbec373d12 Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Signed-off-by: Mathew King <mathewk@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52036 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-04-01soc/amd/cezanne: Add device tree support for I2CRaul E Rangel
This allows the cr50 on guybrush to show up in ACPI. BUG=b:183737011 TEST=Boot OS and see I2C devices initialized Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ifb5679b7bbefbf753217981874bb1bdaef35f6db Reviewed-on: https://review.coreboot.org/c/coreboot/+/51958 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Mathew King <mathewk@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-18soc/amd/cezanne/chip: add soc_acpi_nameFelix Held
We were missing this, so we ran into the scope assert in acpi_device_write_pci_dev for the data fabric PCI devices. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I566791527ba839ba52ec5fa28f0f6c25f547d1da Reviewed-on: https://review.coreboot.org/c/coreboot/+/50815 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-14soc/amd/cezanne: add partial data fabric setupFelix Held
I'm not 100% sure yet if this code will be common for all AMD SoCs, so I'll add a copy for Cezanne for now. This part of the code should probably be reworked after the initial bringup of Cezanne anyway. DF MMIO register configuration at the beginning of data_fabric_set_mmio_np: === Data Fabric MMIO configuration registers === Addresses are shifted to the right by 16 bits. idx control base limit 0 a3 fc00 febf 1 a3 1000000 fffcffff 2 a3 d000 f7ff 3 a0 0 0 4 a3 fed0 fed0 5 a0 0 0 6 a0 0 0 7 a0 0 0 DF MMIO register configuration at the end of data_fabric_set_mmio_np: === Data Fabric MMIO configuration registers === Addresses are shifted to the right by 16 bits. idx control base limit 0 a3 fc00 febf 1 a3 1000000 fffcffff 2 a3 d000 f7ff 3 10a3 fed0 fedf 4 a0 0 0 5 a0 0 0 6 a0 0 0 7 a0 0 0 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia243a0cad311eb210d14d6242c52f599db22515c Reviewed-on: https://review.coreboot.org/c/coreboot/+/50624 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-11soc/amd/cezanne/chip: set device operations for UART MMIO devicesFelix Held
Change-Id: I5df3a61741f05364e2c20725b0b85164b197dbdc Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50484 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-11soc/amd/cezanne: add empty mp_init_cpusFelix Held
Change-Id: I845a7e2cfea58ca08cd2a6f0d884dbbbe1a7bdef Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50483 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-10soc/amd/cezanne/chip: add empty set_mmio_dev_opsFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I2ac5fcd17b6aed464a0d1e55f2860574501f7a8a Reviewed-on: https://review.coreboot.org/c/coreboot/+/50439 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-02-10soc/amd/cezanne/chip: add empty cpu_bus_opsFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I658294c84d64c7de0ccfa74b0e830d787a3a42fe Reviewed-on: https://review.coreboot.org/c/coreboot/+/50438 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-09soc/amd,intel: Drop s3_resume parameter on FSP-S functionsKyösti Mälkki
ACPI S3 is a global state and it is no longer needed to pass it as a parameter. Change-Id: Id0639a47ea65c210b9a79e6ca89cee819e7769b1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50360 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-02-07soc/amd/cezanne/chip: add PCI bus scanningFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I76b0eb4470ac4a48e1caeaf507b5e6c45bb88119 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50333 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-30soc/amd/cezanne: add use result of acpi_is_wakeup_s3() in FSP callsFelix Held
Cezanne doesn't have ACPI support yet, but in this case the function always returns 0, so it can already be used. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1f5e1f31bf1e52988fcef90daf7b93169e21cbb1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50126 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-29soc/amd/cezanne: add empty ramstage FCH supportFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I38c6961b65b89cb57ff80e491bf8973be4e12eeb Reviewed-on: https://review.coreboot.org/c/coreboot/+/50094 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-01-29soc/amd/cezanne/chip: add FSP silicon init driver callFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id3dea23de0c7ce2fca4382e9fd4ec88aecaa55fb Reviewed-on: https://review.coreboot.org/c/coreboot/+/50092 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-28soc/amd/cezanne/chip: add empty SoC device operationsFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic6321223b3b4b8d27ac696fdeeec75fd4bd1e6bb Reviewed-on: https://review.coreboot.org/c/coreboot/+/49952 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-06soc/amd/cezanne: add config.c and minimal chip.hFelix Held
Change-Id: I89f08c201bd7d9a11b186ef960abe9714a76fb97 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48317 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-05soc/amd/cezanne: add skeleton for new SoCFelix Held
This is based on the minimal example code in soc/example/min86 and was adapted to use the AMD non-CAR boot block and the common AMD PCI MMCONF support. In its current state this won't even reach the boot block, but will pass the build bot. The missing parts for that will be added in future patches. This is an attempt to not go the usual route to create a copy of a previous SoC generation and the make changes to the code to work for the new SoC, but to start from a nearly empty directory and then add the actual code stage by stage and component by component. Change-Id: I70aeb9ae010e943abfa667a0ea95c6fa9f15b7f5 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48237 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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